Senior FPGA Engineer II - Network

Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State. Senior FPGA Engineer II - Network In this position, you will be responsible for FPGA designs and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in board-level hardware design is also desirable. The successful candidate will present engineering design review materials to our customers and executive team, as well as participate in proposal‑writing efforts. As such, excellent written and verbal communication skills are required. Salary: $126,000 - $168,500 a year. Full‑time employment offers include company stock options and a generous benefits package including health, dental, vision, HSA, FSA, life, disability and retirement plans. JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS Bachelor of Science (BS) or Master of Science (MS) degree in Electrical Engineering or Computer Engineering from an accredited university or institution. Minimum of 6 years of industry or university research experience in the design, analysis, and implementation of FPGA systems. Production experience in design, implementation, and integration of OSI Layers 2 and 3 networking systems, including protocols such as Ethernet, IP, and MPLS. Experience in networking system design, especially in determining throughput and memory requirements. Expertise in writing and reviewing VHDL. Proficiency in writing and reviewing SystemVerilog for block and system verification. Expertise in FPGA design and verification tools for modern complex FPGA and SoC platforms such as Xilinx Vivado and Siemens Questa. Excellent written and verbal communication skills. PREFERRED EXPERIENCE Deep understanding of network design and an ability to derive requirements based on high‑level objectives. Familiarity with non‑FPGA networking platforms including ASICs and general‑purpose processors. Aerospace design and qualification. Worst‑case analysis, failure method and criticality analyses, and reliability analysis. Experience with board‑level hardware design. Familiarity with communications systems, such as digital signal processing. Experience writing low‑level software for interfacing to FPGA IP. CesiumAstro is an Equal Opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected Veteran Status, or any other characteristic protected by applicable federal, state, or local law. #J-18808-Ljbffr