DFT MBIST Staff Engineer

DFT MBIST Staff Engineer

Location: Remote USA



Work Mode: Remote; must be available to work aligned with PST business hours



Experience: 8+ years in DFT / MBIST



Employment: Contract C2C or W2



Visa: Open to candidates with valid U.S. work authorization

Role Overview

We are looking for an experienced DFT MBIST Staff Engineer with strong hands-on expertise in Synopsys MBIST / SMS for complex SoC designs.

The engineer will own the complete MBIST flow, including insertion, top-level integration, verification, simulation, VecGen pattern generation, diagnostics, and silicon bring-up. The role requires strong debugging capability and the ability to work independently with limited supervision.

Key Responsibilities

• Perform MBIST insertion for complex SoC designs using Synopsys SMS .

• Own MBIST implementation from insertion through verification and sign-off.

• Integrate and verify MBIST architecture at the SoC/top level .

• Develop, execute, and debug MBIST simulations using Synopsys VCS .

• Perform RTL, no-delay gate-level, and timing-aware/with-delay simulations .

• Generate and validate MBIST test patterns using VecGen .

• Debug MBIST insertion, RTL, integration, simulation, and pattern-related issues.

• Implement and debug memory repair schemes including BIRA/BISR and redundancy analysis .

• Support MBIST diagnostics and root-cause analysis of memory failures.

• Support silicon bring-up, characterization, and post-silicon debug .

• Collaborate with DFT, RTL Design, Physical Design, Verification, and Product Engineering teams.

• Develop scripts and document MBIST implementation, verification, and debug flows.

Required Qualifications

• 8+ years of hands-on Design-for-Test (DFT) experience.

• Significant hands-on experience in Memory Built-In Self-Test (MBIST) .

• Strong experience with Synopsys MBIST / SMS , preferably SMS5 and/or SMS6 .

• Strong hands-on experience with Synopsys VCS .

• Experience owning the complete MBIST flow:

  • MBIST insertion

  • Top-level integration

  • Verification

  • Simulation

  • VecGen pattern generation

  • Diagnostics and debug

• Strong understanding of MBIST test algorithms , including March algorithms.

• Experience with BIRA/BISR, redundancy analysis, and spare row/column allocation .

• Experience with no-delay and timing-aware gate-level simulation.

• Experience with complex SoCs containing multiple embedded memory instances.

• Experience supporting silicon bring-up and post-silicon MBIST debug .

• Working knowledge of Verilog/SystemVerilog and standard DFT methodologies.

• Strong root-cause analysis and technical debugging skills.

Technical Skills

MBIST / DFT

• Synopsys MBIST / SMS5 / SMS6

• Memory BIST insertion

• SoC MBIST integration

• MBIST diagnostics

• Memory test algorithms

• March algorithms

• BIRA / BISR

• Memory redundancy and repair

Verification & Simulation

• Synopsys VCS

• RTL simulation

• Gate-Level Simulation

• No-delay simulation

• With-delay / timing-aware simulation

• MBIST simulation and debug

Pattern Generation

• VecGen

• MBIST pattern generation

• Pattern validation and debug

Silicon / SoC

• Silicon bring-up

• Post-silicon debug

• Memory failure analysis

• Complex SoC DFT integration

Programming / Scripting

• Verilog / SystemVerilog
  
  
  
  
  
  
  
  
  #LI-SD1