Elect Design and Analy Engr 3

Location: El Segundo, CA Salary: $70.00 USD Hourly - $80.00 USD Hourly Description: Our client is currently seeking a

Elect Design and Analy Engr 3 Skill Code:64Y-Microelectronics

Work Location: El Segundo, CA

Shifts: 1st shift

Time/Time Zone: 8:00 AM - 4:30 PM

Job Description:

- Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products.

- Develops high-level and detailed designs consistent with requirements and specifications.

- Validates designs through various methods of review, testing and analysis.

- Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.

- Supports Supplier Management with make/buy recommendations and other technical services of limited scope.

- Provides engineering support throughout the lifecycle of the product.

- Investigates emerging technologies to develop concepts for future product designs to meet projected requirements.

- Works under general direction.

* The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores.

* Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity.

* The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families.

* The candidate must have experience troubleshooting static timing violations and creating complex designs coded in HDL (not simply instantiating IP blocks).

* This experience are requirements that will be screened in resume review and interview.

- Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system.

Basic Requirements

2+ years of FPGA design experience;

strong Xilinx/AMD Vivado experience;

Verilog/SystemVerilog proficiency;

Advanced FPGA implementation skills (synthesis, timing closure, constraints)

Preferred Requirements

5+ years of FPGA and/or ASIC design experience;

strong Xilinx/AMD Vivado experience;

Experience with Versal family devices;

Verilog/SystemVerilog HDL proficiency required;

Advanced FPGA implementation skills (synthesis, timing closure, constraints)

Medical, dental, and vision insurance are available to qualified candidates who meet eligibility requirements.
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