Hardware Engineer

Candidates who can work independently in USA without requiring a visa sponsorship are applicable Job Summary We are seeking an experienced Electrical Engineering (EE) Validation Engineer to support hardware validation for next-generation smart glasses within Meta’s Wearables team. The primary focus of this role is to monitor validation progress, review contract manufacturer (CM) test reports, analyze failures, track open issues, and coordinate with EE design partners to drive issues toward resolution. The engineer will guide CM engineers on measurement procedures, develop standard operating procedures (SOPs), review schematics and PCB layouts, and perform hands-on Power Integrity (PI) and Signal Integrity (SI) debugging when required. The ideal candidate will have strong electrical hardware validation experience, excellent data analysis and troubleshooting skills, and the ability to coordinate effectively across manufacturing, hardware design, layout, and firmware teams. The role emphasizes data interpretation, issue tracking, technical guidance, and resolution management under the direction of the FTE validation lead rather than ownership of final validation decisions. Required Qualifications BS/MS in Electrical Engineering. 4+ years of EE hardware validation experience with strong emphasis on power integrity and signal integrity. Proven ability to analyze test data, identify root causes, and drive issues to closure with cross-functional teams. Experience reviewing test reports for correctness, identifying gaps, and driving follow-up actions. Ability to develop test procedures that others execute — clear technical writing, structured SOPs, annotated diagrams. Strong schematic reading skills — trace signal paths, understand power distribution, map circuit function from schematics and datasheets. PCB layout review experience — assess probe access, SI/PI risk, debug strategy. Expert-level knowledge of lab instruments: high-bandwidth oscilloscopes, power rail probes, active/differential probes, current probes, spectrum analyzers. Experience with DC-DC converter characterization and high-speed digital signal measurements. Solid understanding of transmission line theory, impedance matching, and flex PCB signal integrity challenges. Strong communication skills — ability to explain complex EE issues clearly to CM teams and design partners. Preferred Qualifications Experience working with CMs or ODMs in a validation support capacity. Experience with wearable, mobile, or IoT hardware (space-constrained, low-power designs). Familiarity with RF measurement (BLE/WiFi TX power, sensitivity, antenna return loss). Familiarity with proto/EVT/DVT/PVT build cycles and NPI environments. Experience with issue tracking systems and cross-functional coordination in hardware programs. Must-Have Skills 4+ years of EE hardware validation experience with strong emphasis on power integrity and signal integrity. Ability to develop test procedures that others execute — clear technical writing, structured SOPs, annotated diagrams. Strong schematic reading skills — trace signal paths, understand power distribution, map circuit function from schematics and datasheets. PCB layout review experience — assess probe access, SI/PI risk, debug strategy, power regulation circuits.. Expert-level knowledge of lab instruments: high-bandwidth oscilloscopes, power rail probes, active/differential probes, current probes, spectrum analyzers. Nice-to-Have Skills Experience with wearable, mobile, or IoT hardware (space-constrained, low-power designs). Familiarity with proto/EVT/DVT/PVT build cycles and NPI environments. Experience with issue tracking systems and cross-functional coordination in hardware programs. Key Responsibilities Issue Tracking and Closure (~60%) Review CM-generated validation reports to verify data quality, identify anomalies, and ensure pass/fail criteria are correctly applied. Analyze validation failures and determine whether they are caused by measurement errors, design defects, or assembly quality issues. Coordinate with EE design partners to present findings, propose root-cause hypotheses, and support corrective actions. Track issues through resolution, ensuring fixes are validated and closed on time. Facilitate communication between CM, EE design, layout, and firmware teams. Maintain issue trackers and provide regular status updates to the FTE validation lead. Monitor validation milestones and proactively escalated risks and blockers. CM Guidance (~20%) Develop clear, repeatable test procedures and SOPs for CM technicians. Train and guide CM engineers and technicians on measurement techniques, probe placement, fixture usage, and data collection. Define probe points and measurement access strategies using annotated PCB layout markups. Provide technical guidance when measurements produce unexpected results. Establish acceptance criteria and escalation procedures in alignment with the FTE validation lead. Hands-On Measurement and Debug (~20%) Perform PI/SI measurements requiring senior-level technical judgment, including first-article bring-up, intermittent failures, and subtle noise-source investigations. Validate CM measurement setups through correlation measurements. Debug escalated issues that CM engineers cannot resolve independently. Develop measurement methodologies and fixtures for novel circuits or challenging probe-access situations. Support prototype bring-up and characterization during hardware build phases. Technical Knowledge Required Power Integrity (PI) DC-DC converter characterization, including line/load regulation, efficiency, transient response, and output ripple/noise. Power sequencing validation and timing verification against IC specifications. Power-rail stability under varying load conditions and current profiling. Battery charging circuit validation, including charge profiles, protection, and thermal limits. Power distribution network (PDN) concepts, including ground bounce, decoupling strategy, and voltage-droop analysis. Signal Integrity (SI) High-speed interface measurements involving MIPI CSI, SPI, I2C, I2S/PDM, USB, and UART. Signal quality assessment, including rise/fall times, overshoot/undershoot, ringing, and eye diagrams. Crosstalk, reflections, and impedance discontinuities on flex and rigid-flex assemblies. Clock signal quality and jitter characterization. Protocol-level correlation with physical-layer signal issues. Schematic and PCB Layout Competency Read and interpret multi-page schematics to understand circuit topology, power trees, and signal routing. Review rigid and flex PCB layouts to identify optimal probe locations and debug access points. Assess layout risks related to signal integrity and power integrity, including trace routing, return-path continuity, impedance control, and via transitions. Provide layout feedback to design teams to improve testability. #J-18808-Ljbffr