Design Verification Engineer

Job Title: Design Verification Engineer

Location: Dallas, TX (Onsite)

Client: Cyient

Position Type: Contract - C2C/W2



Job Description:
Looking for a senior verification engineers to manage complex subsystem verification with Synopsys peripherals
Hands on experience on testbench development, test plan, coverage and validation for new design
Should be able to hit the ground running in Cadence flows.
Need to be able to handle Auto qualification
Good knowledge on the verification flows, SV and UVM
Perform RTL code coverage and functional coverage, formal analysis
Be responsible for defining the verification strategy and plan for the development
Develop coverage-driven verification test plans
Knowledge on assertion development and coverage improvement
Write test specifications (plans) and create directed and random test cases
Good debugging skills



Responsibilities:
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips.
Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.
Manage complex subsystem verification with Synopsys peripherals- testbench development, coverage and validation and should be able to hit the ground running in Cadence flows.
Need to be able to handle Auto qualification needs
Cadence design flow and Synopsys IP peripherals
8 to 12++ years with good communication and should independently work with the logic team and other functions to drive the tasks.