Staff Design Verification Engineer - Coherent Interconnect (CHI)

About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. Are you ready? To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.Job Description:The RoleSiFive is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem with a strong focus on CHI-based architecture and protocol behavior.In this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, snoop and home-node interactions, credit- and flow-control behavior, and subsystem integration across multiple interface boundaries. This is a horizontal role with broad impact across the coherent interconnect space, requiring strong technical judgment, deep debug ability, and the ability to influence verification strategy beyond an individually assigned block.This is a Staff Engineer individual-contributor role. We are looking for someone who can define verification strategy, identify architectural and verification gaps early, solve difficult protocol and integration problems, and raise the overall quality bar for the broader interconnect verification effort.ResponsibilitiesDrive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and orderingDevelop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, backpressure, flow control, and error handlingVerify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation pathsDefine high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactionsPartner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoffAnalyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test contentImprove methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effortContribute to review quality across specifications, verification plans, coverage closure, and debug strategyMentor other engineers through technical leadership, design reviews, and verification best practicesMinimum QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field7+ years of experience in ASIC or SoC design verificationStrong hands-on experience with SystemVerilog-based verificationStrong understanding of cache-coherent systems, memory subsystems, and on-chip interconnectsDirect experience verifying coherent protocols, with strong preference for CHIStrong understanding of protocol behavior including ordering, snooping, flow control, buffering, arbitration, and error handlingExperience building reusable checkers, scoreboards, assertions, coverage models, and debug infrastructureStrong debugging skills and ability to root-cause issues across specification, RTL, and verification environment layersAbility to work effectively across architecture, design, and verification teams in a fast-moving environmentPreferred QualificationsExperience with ARM CHI or similar high-performance coherent interconnect protocolsExperience verifying large subsystem integration involving coherent caches, bridges, or protocol-conversion pathsExperience with memory consistency, cache coherency, and weak-ordering verification challengesExperience with formal verification, performance-oriented verification, or emulation-assisted debugFamiliarity with Python or other scripting languages used for DV infrastructure and automationExperience mentoring engineers and driving team-wide improvements in verification qualityWhat Success Looks LikeVerification plans are complete, concrete, and aligned to the real architectural and protocol risksCritical CHI and coherent-interconnect bugs are found early, reproduced efficiently, and closed with durable fixesCoverage and test quality improve meaningfully under your ownershipThe coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributionsDesign and architecture teams rely on you as a strong technical partner for difficult protocol, coherency, and integration problemsYou will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.BS/MS Degree in EE, CE or CS5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verificationDeep understand of computer architecture is desiredExperienced developer using Object Oriented Programing principlesIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! Additional Information:This position requires a successful background and reference checks and satisfactory proof of your right to work inUnited States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.SummaryLocation: Boston, Massachusetts, United States; Austin, Texas, United StatesType: Full time