Design Verification Engineer

Senior Asic Verification Engineer

We are seeking experienced Senior Verification Engineers to join our rapidly expanding team, driving breakthrough innovations in cloud and data center infrastructure across both storage and computing. If you are passionate about cutting-edge technology, thrive in fast-paced environments, and want to help shape the next generation of enterprise solutions, we’d love to hear from you.

Responsibilities

• Collaborate closely with design teams to review and understand specifications, architectures, and micro-architectures.
• Define comprehensive test plans and verification strategies.
• Develop block-level and chip-level verification environments.
• Generate and analyze functional and code coverage metrics.
• Execute regressions, debug, and triage failures in simulation environments.
• Validate features and partner with software teams to debug issues in the lab.

Requirements

• BSEE with 7+ years or MSEE with 5+ years of relevant experience.
• Advanced knowledge of ASIC/FPGA verification flows, including simulation, testbench development, and post-silicon validation.
• Strong expertise in SystemVerilog and Verilog.
• Hands-on experience developing testbenches using UVM, OVM, or VMM methodologies.
• Proficiency in C/C++ programming.
• Scripting experience with Python or Perl.
• Familiarity with industry-standard high-speed protocols (PCI Express, DDR, NAND Flash, etc.) is highly desirable.
• Background in computer storage and networking is a plus.
• Excellent communication skills, teamwork mindset, and the ability to take on diverse technical challenges.