FPGA Design Engineer

York is seeking an FPGA Design Engineer to contribute to the development of FPGA solutions for York’s Avionics and Payload Engineering team. In this role, you will collaborate with electrical, software, systems, and test engineers, support architectural decisions, and help deliver mission-ready hardware. Engineers at York take ownership of FPGA modules and verification tasks, contribute to engineering processes, and grow toward broader system-level responsibility. This role will be fully on-site in our Greenwood Village, Colorado office. Responsibilities Participate in the scoping, design, validation, and maintenance of FPGA designs. Develop RTL using SystemVerilog and/or VHDL. Execute simulation and validation at module and integrated system levels. Support system-level integration efforts and collaborative troubleshooting. Debug FPGA designs using simulation tools and lab equipment. Contribute to producing clear and complete technical documentation. Contribute to design reviews and continuous improvement of FPGA development processes. Perform additional mission-supporting engineering tasks as required. What Success Looks Like Within your first months, you will: Take ownership of FPGA modules within mission-critical subsystems. Work with multidisciplinary teams to help deliver flight-qualified designs. Contribute to verification workflows or architectural improvements. Gain deeper experience in York’s avionics technology through hands-on design work. You’ll Thrive Here If You Enjoy solving challenging technical problems collaboratively. Communicate engineering decisions clearly across disciplines. Want a role that blends technical ownership with opportunities to grow into more responsibilities. Want to see your work progress from concept to spacecraft integration. This role will not have direct reports. Required Qualifications B.S. or M.S. in Electrical or Computer Engineering. 2+ years of experience in FPGA design. Solid FPGA/RTL design and debugging skills. Understanding of full product life cycle development. Familiarity with Git or equivalent version control systems. Strong understanding of clocking, reset architecture, and digital design fundamentals. Experience with tools such as Vivado/ChipScope, Libero, or Quartus/SignalTap. Knowledge of verification concepts (UVM, assertions, constrained-random testing). Familiarity with AXI, APB, or other AMBA protocols. Ability to validate FPGA designs using simulation tools and lab equipment. Ability to work both independently and collaboratively. U.S. Citizenship. Ability and willingness to obtain security clearance. Willingness to work full-time in office in Greenwood Village, CO. Preferred Qualifications Exposure to scripting languages (Python, TCL, Make, shell). Familiarity with radiation effects mitigation concepts. Understanding of timing constraints or automated test environments. Exposure to signal processing algorithms or digital signal processing coursework, #J-18808-Ljbffr