Senior ASIC DV Engineer — High-Speed Interconnects & HPC
Avicena Inc.
A pioneering technology firm in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to ensure the functional correctness of high-speed low-power digital integrated circuits. The ideal candidate will have significant experience in ASIC verification, particularly using UVM and SystemVerilog. Responsibilities include developing testbenches, defining verification plans, and debugging complex functional failures. This role is essential in driving innovation for cutting-edge silicon photonics solutions. #J-18808-Ljbffr Avicena Inc.
Vacancy posted 3 days ago
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