DFT Engineer

DFT Engineer

San Jose CA, Irvine CA, San Diego CA

Job Summary:

We are seeking a highly experienced Design for Test (DFT) Engineer to contribute to the development of complex SoC/ASIC designs. This role will focus on DFT planning, integration, testing methodologies, and continuous improvement of DFT flows across chip-level and block level implementations.

Key Responsibilities:

• Develop and implement top-level and block-level DFT plans and integrations

• Utilize Tessent tool flow extensively across DFT processes

• Perform ATPG generation and support ATE interface integration

• Support ATE bring-up and conduct silicon failure analysis and debugging

• Analyze and reduce test time while maintaining high quality standards

• Execute synthesis, STA, and simulation for DFT modes

• Perform formal verification and ensure design correctness

• Implement and manage multi-power domain DFT strategies

• Troubleshoot complex DFT issues and drive continuous DFT flow improvements

Qualifications:

• Bachelor’s degree with 8+ years of experience OR Master’s degree with 9+ years of experience

• Extensive hands-on experience in DFT for ASIC/SoC designs

• Strong expertise in chip-level DFT planning and integration

• Deep knowledge of LBIST (at-speed scan), ATPG, MBIST, and JTAG

• Experience with test time reduction methodologies

• Solid understanding of low power DFT and fault modeling (stuck-at, transition, path delay, IDDQ, etc.)

• Experience with silicon failure analysis and debugging

• Strong knowledge of static timing analysis (STA)

• Experience with DFT simulations including timing considerations

• Familiarity with ASIC/SoC design flows, including low power and multi-power domain designs

• Experience working with Mentor DFT tools or similar EDA tools

If interested, please easy apply on job posting or share your resume at View email address on click.appcast.io .