SR. Principal ASIC Architect / Leader (San Jose)

Astera Labs is scaling the connectivity fabric behind the world's largest AI systems, and we are looking for a Distinguished Engineer to lead architecture for our next generation of high-speed connectivity silicon. You will define system- and chip-level architecture across PCIe, high-speed networking, and Ethernet-based subsystems that power hyperscale AI infrastructure, working at the intersection of silicon, system, and protocol design.

This is a foundational technical leadership role on a hyper-growth team enabling rack-scale AI. You will shape architectural direction for products that hyperscalers depend on for scale-up and scale-out connectivity, own critical tradeoffs across performance, power, latency, area, and cost, and partner deeply with customers and cross-functional teams to translate emerging use cases into industry-leading products

Key Responsibilities

• Define and drive system- and chip-level architecture for high-speed connectivity products spanning PCIe (Gen 6/Gen 7), UALink, UCIe, and Ethernet
• Own micro-architecture specifications and ensure alignment across silicon, system, and software teams
• Contribute to standards-based and custom protocol development for next-generation AI infrastructure
• System Design & Tradeoff Analysis
• Translate hyperscale system requirements into scalable, efficient hardware architectures
• Drive tradeoff analysis across performance, power, latency, area, and cost
• Architect high-speed, low-latency data paths and evaluate integration challenges at the SoC level
• Cross-Functional Execution
• Partner with RTL, Physical Design, Firmware, Validation, and Product Engineering to move architecture from concept to silicon
• Support performance modeling, simulation, and architectural validation
• Engage directly with hyperscale customers and ecosystem partners to understand emerging use cases and requirements
• Technical Influence & Mentorship
• Set technical direction and raise the architecture bar across the connectivity portfolio
• Mentor senior engineers and grow architectural depth across the R&D organization

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 15+ years of experience in semiconductor architecture, ASIC design, or system engineering
• Strong expertise in PCIe architecture (Gen 4/5/6+) and its broader ecosystem
• Deep understanding of networking and Ethernet technologies (25G/50G/100G/400G and beyond)
• Proven experience architecting high-speed, low-latency data paths and SoC-level integration
• Track record of driving architecture across the full chip development lifecycle, with strong analytical, tradeoff, and cross-domain collaboration skills

Preferred Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field
• Experience with UALink, NVLink, UCIe, or other advanced interconnect protocols
• Background in AI/ML infrastructure, data center systems, or hyperscaler environments
• Experience with SerDes-based systems, high-speed PHY integration, switching, or RDMA technologies
• Familiarity with performance modeling tools, architectural simulators, and power/performance optimization at the system level