Postdoctoral Fellow (PREP0004276)

General Description PREP Research Associate CHIPS Funded Project. This position is part of the National Institute of Standards (NIST) Professional Research Experience (PREP) program. NIST recognizes that its research staff may wish to collaborate with researchers at academic institutions on specific projects of mutual interest and thus requires that such institutions be the recipients of a PREP award. The PREP program requires staff from a wide range of backgrounds to work on scientific research in many areas. Employees in this position will perform technical work that underpins the scientific research of the collaboration. Research Title: Metrology of Materials, Surfaces, and Processes for Semiconductor Advanced Packaging We are seeking a highly motivated researcher to advance measurement science for next‑generation hybrid advanced packaging. This role will contribute to the development of novel surface and materials metrology methods that enable predictive control of bonding processes and heterogeneous integration. The successful candidate will work within the Nanophotonics project to help establish the quantitative foundations needed for reliable, high‑density microelectronic assembly, supporting national efforts to strengthen U.S. leadership in semiconductor manufacturing and advanced packaging technologies. Responsibilities Fabricate Si, SiO 2 , SiN chips for flip‑chip fusion and hybrid bonding experiments. Optimize and maintain fabrication processes, including chip handling and cleaning protocols. Perform surface and thin film characterization of chips used for flip‑chip bonding experiments. Characterization techniques include AFM, optical inspection, IR transmission microscopy, spectroscopic ellipsometry, SEM and others. Closely coordinate with teams performing materials characterization, bond strength testing and modeling. Qualifications Necessary Qualifications: PhD in physics, electrical engineering, materials science, or a related field. Significant experience, including process development, in semiconductor device fabrication, wafer cleaning and handling, lithography mask layout, optical or electron beam lithography, RIE, ICP RIE, PVD, CVD, ALD, wet etching, and characterization techniques such as ellipsometry, profilometry, optical microscopy, SEM and AFM. Proficiency in programming languages, such as Python, Java or Matlab. Excellent communication skills and ability to work effectively in a team. US citizenship strongly preferred. Desirable Qualifications: Experience with flip‑chip fusion and/or hybrid bonding processes. Experience with XPS, UPS, FTIR, Raman, photoluminescence, and other relevant modalities of spectroscopy. Familiarity with silicon electronic, photonic or optoelectronic device processing. Experience with custom infrared microscopy and optical measurement setups. Experience with III‑V compound semiconductor process development and device fabrication. Experience with optoelectronic device characterization. Experience with photonic and optoelectronic device simulation software, such as Lumerical, Tidy3d, or COMSOL. Salary Range The referenced salary range represents the minimum and maximum salaries for this position and is based on Johns Hopkins University's good faith belief at the time of posting. The actual compensation offered may vary depending on location, skills, experience and other factors. Total Rewards Johns Hopkins offers a total rewards package that supports our employees' health, life, career and retirement. More information can be found at: Equal Opportunity Employer The Johns Hopkins University is committed to equal opportunity for its faculty, staff, and students. To that end, the university does not discriminate on the basis of sex, gender, marital status, pregnancy, race, color, ethnicity, national origin, age, disability, religion, sexual orientation, gender identity or expression, veteran status or other legally protected characteristic. EEO is the Law #J-18808-Ljbffr The American Ceramic Society