Silicon Substrate Design Engineer

We are seeking a highly skilled and detail-oriented Silicon Substrate Design Engineer to drive the physical design and layout implementation of next-generation 2D, 2.5D and 3D heterogeneous packaging architectures. Specializing in Silicon Interposer and Redistribution Layer (RDL) technologies, you will collaborate closely with ASIC architecture, foundry partners, OSATs, and Signal/Power Integrity (SI/PI) teams to deliver robust, high-density interconnect solutions for high-performance computing (HPC), AI accelerators, and high-speed networking applications. Skills : IC Package Design & 2D, 2.5D & 3D packaging architectures is a must Key Responsibilities Physical Layout & Routing: Own the end-to-end physical design, floor planning, and layout of passive/active silicon interposers and high-density RDL fan-out packages. High-Density Interconnects: Execute complex routing for ultra-fine-pitch microbumps, C4 bumps, TSVs (Through-Silicon Vias), microvias, and pillar structures. Interface Implementation: Route critical high-speed, high-bandwidth interfaces such as HBM, PCIe Gen 5/Gen 6, and die-to-die interfaces with stringent impedance controls. Design Optimization: Actively drive die-package-board co-optimization (DPCO) by mapping bump assignments and floorplans across multiple disparate chiplets. Constraint Implementation: Incorporate layout constraints provided by SI/PI teams, optimizing power delivery networks (PDN) and implementing shielding strategies to minimize crosstalk, insertion loss, and IR drop. Verification: Run and resolve comprehensive physical verification checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), connectivity, and antenna rules. DFM & Yield: Collaborate with leading silicon foundries and OSATs to ensure strict alignment with Design for Manufacturing (DFM), Design for Assembly (DFA), and reliability standards to maximize production yields. Required Skills & Qualifications Technical Expertise Deep understanding of 2.5D/3D advanced packaging architectures, wafer-level packaging (WLP), and substrate technologies. Mastery of layout routing constraints, stack‑up optimization, and silicon processing limits (e.g., fine-line/space lithography down to sub‑micron scales for RDL). Solid grasp of electromagnetic and transmission line fundamentals, signal integrity constraints, and thermal‑mechanical stress factors in silicon‑interposer assemblies. Tool & EDA Proficiency Extensive hands‑on experience with advanced IC packaging and IC layout tools, including: Verification: Siemens EDA Calibre, Ansys (HFSS/SIwave for layout review), and IC Validator. Soft Skills & Experience Excellent cross‑functional communication skills, with a proven ability to bridge gaps between silicon design teams and manufacturing foundries. Strong debugging and problem‑solving skills when addressing complex DRC violations and multi‑die routing bottlenecks. Education & Experience Requirements Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Electronics, Microelectronics, Materials Science, or a closely related field. Experience (Engineer): 3+ years of experience in silicon physical design or IC package layout. Experience (Senior/Staff Engineer): 6–10+ years of hands‑on experience delivering production‑ready 2.5D/3D interposer or high‑density fan‑out (HDFO) designs from concept to tape‑out. #J-18808-Ljbffr Yochana