Senior FPGA Silicon Validation Engineer

A leading provider of programmable logic solutions in San Jose seeks a Silicon Design Validation Engineer with over 8 years of experience. The successful candidate will validate FPGA building blocks and characterize high-speed interface performance. Responsibilities include developing validation plans, analyzing data, and leading a small team. The role offers a salary range of $144,000 to $180,000 plus bonus and equity options, underscoring our commitment to employee success and innovation. #J-18808-Ljbffr Lattice