RTL Design Engineer — CPU Core & Verification
Intel
Intel in Austin, TX seeks a College Grad to design RTL and write Verilog/SystemVerilog for a CPU IP block used in full-chip designs. You will contribute to architecture and microarchitecture features, and work to meet power, performance, and timing goals. You will review verification plans, resolve RTL issues, document MAS specifications, and assist SoC customers to ensure high-quality CPU integration across designs. #J-18808-Ljbffr Intel
Vacancy posted 5 days ago
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Correct Designs
Austin, TX4 days ago
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