ASIC FPGA Engineer Entry Level

Responsibilities for this Position

ASIC FPGA Engineer Entry Level

ID: 2026-75010
US-ID-Boise US-UT-Salt Lake City
Required Clearance: Secret, obtainable within reasonable time based on requirements
Posted Date: 9/17/2026
Category: Engineering-Hardware
Employment Type: College
Hiring Company: General Dynamics Mission Systems, Inc.

Basic Qualifications

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field.

CLEARANCE REQUIREMENTS:
[Department of Defense Secret security clearance is preferred at time of hire.] Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

Role and Position Objectives:

As a hardware engineer for our Idaho Scientific group, youll be a member of a cross functional team responsible for designing and deploying secure system solutions through novel CPU design, crypto cores, purpose-built system-on-a-chip architectures, and hardened operating systems. Our solutions are the foundation for how military systems will remain safe and secure in the conflicts of the future.

Duties and Tasks:
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
Determines architecture, system simulation and detailed design approach
Defines module interfaces and all aspects of device design and simulation
Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization
Creates test and simulation plans that establish functional criteria
Verifies test results and analyzes performance
May also review vendor capabilities, foundry technologies, device libraries and simulation tools

What Sets You Apart:
Working knowledge and able to perform all responsibilities associated with the position
Grasps and applies new information quickly
Ability to handle more complex assignments with experience
Shows initiative on assignments, and professionally executes projects with little direction
Good written and verbal communication skills
Ability to recognize and clearly report information relevant to sound ASIC/FPGA design topics
Working knowledge of Microsoft Office applications
Identifies opportunities to apply AI for continuous improvement and innovation

#LI-Hybrid

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $85,239.00 - USD $94,562.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

PI287158421