Senior Mask Design Engineer
NVIDIA Gruppe
Senior Mask Layout Design Engineer You will be part of a team responsible for handling complex mixed-signal circuit designs. Responsibilities The role entails working collaboratively and multifunctionally with a multidisciplinary team of photonics, CMOS, electronics, and systems engineers. Perform physical layout for mixed-signal functions such as PLLs, high‑speed I/O circuits, general I/O, and ESD structure designs in innovative sub‑micron CMOS technologies using Cadence tools. Work with ASIC and mixed‑signal engineers to customize designs for integration in VLSI products. Perform floor planning, custom layout, and verify against design rules and schematics. Handle fill, post‑processing, DRC mitigation, and foundry interactions. Qualifications BS in Electrical Engineering (or equivalent experience). At least 6+ years of hands‑on layout design experience. Deep understanding of analog circuit layout concepts in sub‑micron CMOS technologies. Validated experience with Cadence custom circuit design tools, particularly Virtuoso. Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield. Ability to work optimally in a team with strong interpersonal skills and positive energy. Proficiency in scripting languages such as Perl, Python, and knowledge of DRC and LVS checking flows. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $132,000 – $207,000 USD for Level4, and $148,000 – $235,750 USD for Level5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until May31,2026. NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. #J-18808-Ljbffr
$132k - $207k
...Responsibilities Collaborate with a multi-disciplinary team of circuit designers and mask designers. Perform physical layout for digital and mixed‑... ...using Cadence tools. Work with ASIC and mixed‑signal engineers to customize designs for integration in VLSI products....Senior$132k - $207k
Senior Mask Design Engineer - Hardware page is loaded## Senior Mask Design Engineer - Hardwarelocations: US, CA, Santa Clara: US, CA, Remotetime type: Full timeposted on: Posted Yesterdayjob requisition id: JR2016125**What you'll be doing:*** Performing physical layout...Senior$132k - $207k
...A leading technology firm in Santa Clara is seeking a Senior Mask Design Engineer to perform physical layouts for analog components using Cadence tools. The ideal candidate should have over 7 years of experience in Mask and Layout Design, particularly with sub-micron CMOS...Senior- ...NVIDIA Corporation is looking for an experienced layout designer in Santa Clara, California. You will collaborate with a team of engineers to execute precise physical layouts for advanced mixed-signal functions, utilizing Cadence tools while adhering to strict design...Senior
$132k - $207k
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...Senior Design Engineer, Coherent High Speed Interconnect page is loaded## Senior Design Engineer, Coherent High Speed Interconnectlocations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2015857NVIDIA is looking for a Senior Design...Senior- Intel Corporation is looking for a skilled Clocking Design Engineer to contribute to their advanced CPU designs in Austin, Texas. This role involves implementing custom clock solutions and collaborating across various engineering teams. Candidates should have a relevant...Senior
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NVIDIA Gruppe in Santa Clara is looking for a talented engineer to join their Clocks team. This role involves architecting clock domains... ...Engineering or equivalent, 3+ years of experience in RTL design, strong skills in Python, and excellent interpersonal abilities...Senior- A leading technology company in Santa Clara is seeking an experienced Compiler Circuit Design Engineer to contribute to innovative ASIC design. In this role, you will drive the development of SRAM and register files, collaborate with compiler vendors, and integrate new...Senior
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A leading technology company in California is seeking a senior engineer for their wireless silicon development team. The role involves generating... ...and utilizing scripting skills, with a focus on ASIC design. Candidates must have a BS degree and at least 10 years of experience...Senior$160k - $210k
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YOH Services LLC is seeking a Sr. High-Speed SI/PI Design Engineer in Santa Clara, California. The role involves modeling and simulating high-speed interfaces, designing Power Delivery Networks, and collaborating with package layout engineers. The ideal candidate will have...Senior- ...in the business of optoelectronic device design, production, packaging, and applications.... ...speed photodiode (100G/lane and above) · Mask layout generation · Data analysis to... ...closely with internal and external epitaxial engineer, integration engineer, packaging/testing...SeniorH1bVisa sponsorship
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