Senior Director, AMS Layout Engineering

Why join Upscale, Inc. 

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

About the Role

We are building a world-class SerDes engineering team to enable next-generation AI data center connectivity. As Senior Director of AMS Layout Engineering, you will lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation SerDes technologies.

This is a strategic technical leadership role for an experienced AMS layout leader who combines deep expertise in advanced-node analog layout, a strong understanding of high-speed PHY design challenges, and a proven track record of building and developing high-performing engineering teams.

You will partner closely with analog design, digital design, process technology, and silicon validation teams to translate demanding electrical and physical requirements into robust, high-performance silicon implementations. You will also establish the methodologies, design practices, and organizational capabilities needed to scale our SerDes development efforts.

Responsibilities:

• Technical Leadership: Lead AMS layout engineering for advanced high-speed SerDes PHYs, driving physical implementation, optimization, and sign-off across critical analog and mixed-signal circuit blocks.
• Advanced-Node Expertise: Drive layout solutions at advanced nodes, addressing increasingly complex design rules, restrictive patterning requirements, parasitic effects, device matching, signal integrity, power integrity, and electromigration.
• High-Speed PHY Optimization: Partner with circuit designers to optimize layout-sensitive performance, including bandwidth, jitter, noise, matching, power consumption, and overall silicon robustness at 100G+ per-lane data rates.
• Physical Design Methodology: Establish and improve layout methodologies, design guidelines, verification flows, and quality standards to enable predictable execution and first-silicon success.
• Cross-Functional Collaboration: Work closely with AMS design, digital implementation, technology, package, and silicon validation teams to resolve complex integration challenges and deliver competitive silicon.
• Organization Building: Build and scale a strong AMS layout organization through strategic hiring, technical mentorship, talent development, and succession planning.
• Execution and Delivery: Drive project planning, resource allocation, technical reviews, and execution across multiple concurrent development efforts while maintaining high standards for quality, schedule, and engineering productivity.
• Engineering Excellence: Foster a culture of technical depth, accountability, continuous improvement, and collaboration across geographically distributed teams.

Qualifications: 

• BS, MS, or PhD in Electrical Engineering, Microelectronics, or a related field.
• Proven experience delivering advanced-node analog or mixed-signal designs at 5nm or below, or equivalent leading-edge process technologies.
• Strong understanding of layout techniques for high-speed SerDes and PHY circuits, including high-speed transmitters, receivers, clocking circuits, PLLs, DLLs, and other timing-critical analog blocks.
• Demonstrated understanding of advanced process design rules, parasitic extraction, physical verification, device matching, signal integrity, and power integrity.
• Experience leading complex silicon development programs from early floorplanning and layout planning through physical verification, tape-out, and silicon bring-up.
• Proven ability to recruit, develop, mentor, and retain strong engineering talent while building an effective and collaborative team.
• Excellent communication skills and the ability to influence technical decisions across multidisciplinary engineering organizations.

Preferred Qualifications: 

• Direct experience developing and delivering 100G+ per-lane SerDes PHYs
• Experience leading AMS layout teams for high-speed connectivity products targeting AI accelerators, high-performance computing, networking, or advanced data center applications.
• Deep expertise in layout-sensitive circuit optimization, including parasitic management, coupling and crosstalk mitigation, clock distribution, supply integrity, and electromagnetic interactions.
• Experience with advanced packaging, chiplet integration, and high-bandwidth die-to-die interfaces.
• A strong track record of establishing scalable engineering methodologies and delivering complex, high-performance silicon across multiple technology generations.
• Experience building engineering teams in a fast-paced, high-growth semiconductor organization.