Senior Verification Engineer

Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP (digital signal processing) solutions for cloud and AI infrastructure, a foundational technology that enables faster and more efficient transmission within and between AI data centers. The firm is empowering the future of AI infrastructure and cloud connectivity with DSP innovations. The firm recently came out of stealth with $180MM funding and is backed by storied venture investors including Kleiner Perkins, Spark Capital, Mayfield and Fidelity Investments. Responsibilities Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. Build verification environments using SystemVerilog and UVM. Identify and write all types of coverage measures for corner‑cases. Debug the functionality with design engineers. Perform coverage collection and follow the metrics to close the full functionality. Requirements 10+ years of experience; at least 7 years of experience in verification – a must. In-depth knowledge in VLSI verification flow, languages and concepts – a must; performed at least 2 or more full block/system verification cycles. Deep experience in building verification environments using SystemVerilog and UVM or specman or systemC. Experience in data path or data protocols, specifically Ethernet – preferred. Verification using one of the known methodologies (eRM, UVM, OVM). Nice to Haves Track record in identifying and writing all types of coverage measures for corner‑cases. Planned and performed the verification of digital design blocks according to the design specification and interacting with design engineers. Collaborative environment: Ability to verify Analog/mixed-signal designs in a collaborative. Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams. #J-18808-Ljbffr