Senior Design Verification Engineer

Experienced Design Verification Engineer to support functional and system-level verification of complex designs. This role requires a strong multi-level design verification background, with experience spanning C++ functional validation and SystemVerilog/UVM-based RTL verification . The ideal candidate will be comfortable debugging issues across both software and RTL environments, analyzing coverage, and ensuring complete verification as designs move through different levels of implementation. Key Responsibilities Perform functional validation and design verification across multiple levels of the system. Develop and execute verification using SystemVerilog and UVM for RTL functionality, timing, and system interactions. Test and validate design behavior using C++ and RTL-based verification environments . Debug complex issues across C++ models and RTL implementations to identify functional and timing problems. Perform coverage analysis and coverage closure to identify verification gaps and improve test completeness. Investigate discrepancies between different levels of the design and help ensure consistent behavior throughout the design transformation process. Collaborate with design and engineering teams to reproduce, isolate, and resolve defects. Qualifications Strong experience in Design Verification (DV) and functional validation. Hands-on experience with SystemVerilog and UVM . Strong understanding of RTL verification, timing, and system-level interactions . Experience working with C++ verification or functional models . Strong debugging and problem-solving skills across both C++ and RTL domains . Experience with functional and code coverage analysis and coverage closure . Ability to work effectively in a remote engineering environment during Pacific Time working hours . #J-18808-Ljbffr