DFx Engineer

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high‑performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us. Role and Responsibilities As a seasoned DFx engineer, you will be involved across the entire spectrum of activities from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug. You will be working on IP‑level projects (GPU, system interconnect) in bleeding‑edge processes that continually drive high test‑coverage requirements. This position is local to Austin, TX only. Understand SOC requirements and project milestones to help define a DFT architecture that optimally balances coverage, test‑time, and execution. Create a detailed implementation spec which documents details of the architecture including SOC‑level interface, clock design, and support of various test/debug modes. Close on the spec with stakeholders including DFX, RTL, SOC, STA, and PD teams. Implement DFT scan: RTL creation, lint, timing constraints, ATPG and simulation. Benchmark test coverage and test‑time to ensure they meet expectations. Drive toward continuing DFX excellence: improving test coverage, minimizing test‑time, and exploring tools and methods that improve execution efficiency. Build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve silicon issues including test‑escapes and yield loss. Skills and Qualifications 10+ years’ experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years’ experience with a Master’s degree, or 6+ years’ experience with a PhD. 10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU/GPU) and/or SOC projects. Demonstrated ability to architect DFT solutions from scratch on at least one project, and to create detailed specifications that can be used as a blueprint for implementation. Detailed understanding of test coverage requirements across various scan modes, especially as they pertain to bleeding‑edge process nodes. Strong familiarity with RTL coding & STA with working knowledge of Physical Design. Familiarity with multi‑voltage and multi‑clocking domain implementation is a plus. Exposure to advanced approaches including hierarchical DFT and streaming fabric. Strong post‑silicon experience as it relates to debugging silicon behavior and test‑escape issues. Able to solve difficult problems with creative solutions or analysis. Crisp written and oral communication skills, including working with global stakeholders. Thrives in a fast‑paced environment, e.g., yearly project tapeouts. Total Rewards Base pay ranges from $180,200 to $270,400. The role is exempt and not eligible for overtime pay under the FLSA. Benefits include medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance, paid time off, student loan program, wellness incentives, and potential eligibility for long‑term incentive plans and relocation. U.S. Export Control This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export‑controlled information or be eligible to receive government authorization to access export‑controlled information. Trade Secrets By submitting an application, applicants agree not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information belonging to any current or previous employer or other person or entity. Equal Employment Opportunity Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law. #J-18808-Ljbffr Samsung Semiconductor