Senior Avionics FPGA Design & Verification Engineer - TeraWave
$156.8k - $219.52kBlue Origin
Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. As part of the Spacecraft Systems team, you will develop vehicle avionics with Field Programmable Gate Arrays (FPGA) at the core for vehicle control and operation with processing and integration of various system interfaces. As part of the development team, you will design, develop, and verify high-performance avionics hardware for space flight vehicles. You will drive requirements definition, modeling, analysis, design, test, and production release of on-vehicle systems. Your responsibilities will encompass electronic requirements, architecture concepts, detailed design development, design verification and test. In addition, you will follow avionics designs through formal verification, environmental qualification, release, and participate in integration and flight support activities. Responsibilities include but are not limited to:
- Design and develop digital hardware architectures for high reliability satellite avionics
- Create and implement RTL code for critical SoC blocks and interfaces
- Contribute to architecture optimization for performance, power, and cost trade-offs
- Collaborate on design verification to ensure robust and reliable designs
- Participate in advanced verification techniques: Assertion-Based Verification, Universal Verification Methodology, and/or Constrained Random Verification
- Support prototype development for early validation
- Document design specifications, architecture decisions, and implementation details
- Participate in design reviews and technical discussions with cross-functional teams
- Troubleshoot and debug complex digital design issues
- Implement interfaces between digital hardware and firmware/software components
- Research and evaluate new architectural approaches to meet evolving requirements
- B.S. or higher in Electrical Engineering, Computer Engineering, or a related discipline
- 7+ years of experience in digital design and SoC architecture
- Proficiency in SystemVerilog or Verilog for RTL implementation
- Experience with SoC integration and interface design
- Understanding of digital timing and synchronization concepts
- Knowledge of industry-standard bus protocols (AXI, AHB, etc.)
- Familiarity with synthesis tools and RTL-to-gates methodology
- Experience with simulation and debugging of complex digital systems
- Strong background in Field Programmable Gate Arrays (FPGA) and FPGA tool flow
- Solid knowledge of simulation-based test using Questasim, and evaluation of code coverage metrics
Preferred Qualifications
- Master's or PhD in Electrical Engineering, Computer Engineering, or related discipline
- Experience developing avionics or electronics for space, aerospace, or other harsh-environment/mission-critical applications
- Experience with radiation-tolerant or radiation-hardened FPGA/SoC design techniques (e.g., TMR, SEU/SEL mitigation, error detection and correction)
- Hands-on experience with space-grade or aerospace-qualified FPGAs (e.g., Xilinx/AMD Versal, RTG4, Microsemi/Microchip PolarFire)
- Proficiency with Universal Verification Methodology (UVM), Constrained Random Verification, and/or Assertion-Based Verification (SVA) in a production design flow
- Experience with high-speed serial interfaces (SpaceWire, SERDES, JESD204, PCIe, etc.) relevant to satellite or optical communication payloads
- Familiarity with safety-critical or high-reliability development standards (e.g., DO-254, MIL-STD-883, NASA EEE-INST-002)
- Experience with hardware/software co-design and firmware integration, including embedded processor cores (e.g., MicroBlaze, ARM Cortex, RISC-V soft cores)
- Scripting and automation experience (Python, Tcl, Perl) to support verification, regression testing, and design flow automation
- Experience with formal verification methods and tools
- Required for all positions: Blue’s Standard Background Check
- Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation
- Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training.
- Required for certain Job Profiles: Ability to obtain and maintain Merchant Mariner Credential, which includes pre-employment and random drug testing as well as DOT physical
- Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
- Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
$156.8k - $219.52k
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...the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6... ...for critical operations worldwide. The ASIC Verification Engineer leads verification of complex digital subsystems...SeniorPermanent employmentFull timeTemporary workLocal areaWorldwide- ...California. Strong experience in FPGA design Track record in radio and... ...algorithms, DSP Hardware verification FPGA synthesis RTL Coding and... ...Simulation If you are an FPGA Engineer looking to take a... ...synthesis RTL Coding and Simulation Seniority level Mid-Senior level Employment...FpgaSeniorFull time3 days per week
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...the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6... ...operations worldwide. The Principal ASIC Verification Engineer serves as a technical authority for verification...SuggestedPermanent employmentFull timeTemporary workLocal areaWorldwide- ...Title: Sr. FPGA Design Engineer Location: Redmond Term: Contract (possible Perm) Duration: Long-Term Contractor/Perm Start Date: ASAP 10+Years experience: FPGA/Modem Design Ultrascale+ & Versal VHDL & SystemVerilog Design and Simulate High-speed Serdes Solid scripting...FpgaSeniorPermanent employmentContract workFor contractorsImmediate start
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