DFT Engineer

Overview Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > ASICS Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Responsibilities DFT pattern generation, coverage analysis and debug. Run and debug gate level simulations. Deploy DFT methodologies to reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. Support both pre-silicon and post-silicon activities in the DFT domain. Preferred Qualifications 10+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is required Understanding of core-based test methodology and scan isolation. Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware. Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing. Experience with industry EDA ATPG and insertion tools. Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. 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Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay Range And Other Compensation & Benefits $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our benefits package is designed to support your success at work, at home, and at play. Your recruiter will discuss details about Qualcomm benefits. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr