Sr. Engineering Manager

Sr. Engineering Manager/Site Manager Onsite required in Portland, OR. Salary Range: $200k-$250k Corporate Introduction As a founding premier member of RISC-V International, Andes is the leading supplier and technological innovator in the RISC-V market with a wide range of processor products fulfilling performance/area/power requirements. Andes has perfected the technology of quick and efficient design of custom extensions to its proprietary CPU. With over 10 billion cumulative shipments of SoCs embedded with Andes CPU IP, Andes products have covered audio, Bluetooth, gaming, GPS, machine learning, MCU and more. Our design innovation enables us to quickly adapt to the rapidly evolving demands of RISC-V customers. Founded in 2005, Andes yearly revenue has tripled in size from $10 million in 2017 to $30 million in 2021. Andes was ranked among "100 Fastest-Growing Companies" in 2020 by CommonWealth Magazine. Headquartered in Taiwan, Andes is capitalizing on its current growth by branching out its offices to the US and Canada to expand on its current 300 employee workforce. Employees are valued as the key ingredient to the success of the company. They will have an opportunity to create a strong and positive impact on the company, where feedback is encouraged and implemented. Role This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to lead a team of CPU designers and DV engineers and build the next-generation of RISC-V CPUs. As a leader of this team, you will help guide design methodologies, analyze problems and devise best QoR solutions. Your responsibilities will include management of schedules, resources, hiring and office-site administrative tasks. Ideal candidates will be dynamic and have a profound passion for technical advances, CPU architecture, and leadership, coupled with a strong commitment to fostering a nurturing and supportive work environment for a diverse team consisting of both seasoned veterans and fresh-faced junior new graduates. Daily activities include: Monitor production schedules, resource allocation, and workflow to ensure timely delivery of CPU IP. Lead and motivate a team of engineers, technicians, and support staff, fostering a positive work environment. Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them Technical Documentation Responsible for efficiently working with multiple time zones, demonstrating effective autonomous management skills, and willingness to engage in late evening calls as required. Technical Requirements: Bachelor’s or Master’s degree in related engineering field 0-15 years experience in CPU design and engineering 8+ years of managerial and administrative experience Proven experience within the semiconductor or CPU IP industry. Strong experience in operations management or site management Strong knowledge of CPU IP development processes, including RTL design, and synthesis Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) Experience using Verilog, System Verilog Strong mastery using Unix and scripting languages such as make, shell, perl or python Strong communication skills Excellent leadership and team management skills, with the ability to inspire and motivate a diverse team. Proven track record of long-term commitments, and a strong desire to contribute to our company’s growth and success over an extended period of time. Desirable Skills: Bilingual with Mandarin #J-18808-Ljbffr