Senior Silicon Validation Engineer - High-Speed SerDes
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Ayar Labs is seeking a Principal Engineer, Silicon Validation in San Jose. You will lead the validation strategy for electronic-photonic SoCs, drive first silicon bring-up, and oversee post-silicon validation of SerDes interfaces and mixed-signal blocks.
You will mentor engineers and produce comprehensive signoff documentation. Applicants should have a strong background in high-speed SerDes validation, lab automation with Python, and familiarity with Ethernet/PCIe standards.
#J-18808-Ljbffr Jobleads-USVacancy posted 2 hours ago
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