Senior OSAT Engineer (Part-Time, Contract)

Responsibilities Lead technical engagement with OSAT suppliers on assembly and test process development, yield ramp, quality improvement, and volume manufacturing readiness. Drive new product introduction (NPI) from engineering builds through production release, ensuring OSAT capability meets electrical/thermal/mechanical requirements for FPGA and SoC products. Optimize packaging and test architectures for performance, cost, and reliability: flip‑chip BGA, high‑pin‑count packages, substrate technologies, wafer‑level solutions, burn‑in/FT coverage. Monitor and improve backend yield performance using data‑driven analysis; identify systemic issues and lead root‑cause corrective actions. Partner with Test Engineering, Packaging, Product Engineering, DFM, and Quality teams on process optimization, failure analysis, and manufacturability improvements. Implement and maintain process control systems, SPC methodologies, automation improvements, and lean manufacturing principles at OSAT. Support cost reduction initiatives including BOM optimization, process simplification, and cycle time improvements. Track supplier performance metrics (yield, DPPM, cost, cycle time, OEE) and provide updates with risk assessments and mitigation plans. Lead or support reliability testing and package qualification activities aligned to industry standards (JEDEC, IPC, AEC‑Q). Maintain strong technical relationship and communication cadence with OSAT partners to ensure transparency, collaboration, and escalation management. Qualifications Minimum Requirements Bachelor’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field. 10+ years of semiconductor assembly, packaging, or test engineering experience. Hands‑on experience with OSAT manufacturing environments, including wafer finishing, substrate attach, interconnect packaging, test, and burn‑in. Strong technical understanding of backend manufacturing flows: flip‑chip, wire bond, underfill, molding, final test, reliability stress and analysis. Proven ability to analyze yield, reliability, and cost data to drive engineering decisions and improvements. Demonstrated success working with international suppliers and cross‑functional teams. Strong written and verbal communication skills, including technical reporting and supplier engagement. Preferred Qualifications FPGA, ASIC, or SoC backend experience, particularly high‑pin‑count or high‑power devices. Experience in automotive or high‑reliability product qualifications (AEC‑Q / ISO standards). Familiarity with advanced packaging: 2.5D/3D, fan‑out WLP, heterogeneous integration. Knowledge of supply chain risk mitigation, dual sourcing, and volume scaling strategies. Experience with automation, traceability systems, and smart factory/manufacturing analytics. Salary Range Pay range for Bay Area, California only: $159,700 - $230,000 USD. This is a part‑time, hourly position that pays the equivalent hourly rate of the below salary range. Job Type Regular Shift: Shift 1 (United States of America). Primary Location: San Jose, California, United States. Additional Locations: posting statement indicates all qualified applicants will receive consideration for employment without regard to protected characteristics. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr