Senior Staff Physical Design Engineer: AI-Driven Signoff
Jobleads-US
Synopsys, Inc. seeks an experienced ASIC physical design engineer to drive timing closure for advanced-node designs and lead signoff readiness across block, subsystem, and full-chip implementations.
You will build repeatable design flows using TCL, Python, and Perl, and work with PrimeTime, ICC2, Fusion Compiler, and Cadence tools, collaborating with CAD, verification, and frontend teams to ship silicon on schedule.
#J-18808-Ljbffr Jobleads-USVacancy posted 1 day ago
Similar jobs that could be interesting for youBased on the Senior Staff Physical Design Engineer: AI-Driven Signoff in Sunnyvale, CA vacancy
- ...is the leader in engineering solutions from silicon... ...rapidly innovate AI-powered products.... ...-leading silicon design, IP, simulation and... ...of advanced-node physical design, where a 50... ...three months before signoff, and you have... ...machine learning-driven design optimization...Senior
- ...discovery to powering AI and the technologies people... ...to advanced-node physical design for complex ASIC and SoC... ..., timing closure, signoff, and design optimization... ...technology, and product engineering teams, you will help... ...automation, and data-driven design solutions that...Senior
Advanced Micro Devices , Inc.
Santa Clara, CA1 day ago $136k - $218.5k
...tapping into the unlimited potential of AI to define the next era of computing.... ...We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team... ..., routing, physical optimization, signoff, and ECOs. Demonstrated success...SeniorFull time$82.08k - $193.44k
...At Capgemini Engineering, the world leader in engineering... ...considering As a Physical Design Engineer , you will work... ..., including design signoff, foundry interaction,... ...experience and skills, Seniority and performance, Market... ...capabilities in AI, generative AI, cloud...SeniorFull timeLocal areaCapgemini
Santa Clara, CAmore than 2 months ago- ...Synopsys, Inc. is seeking an experienced ASIC physical design engineer in Sunnyvale, CA. You will drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs across block, subsystem, and chip levels. You will develop methodologies...Suggested
$200k
...Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely... ...SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies....SeniorFull timeFlexible hoursVelaura AI
Santa Clara, CA7 days ago$141.91k - $269.1k
...leadership for the AI era. With a... ..., a world-class design ecosystem, and an... ...Government (ADG) - The Senior DFT Logic Design Engineer provides... ...and mindset.Self-driven and results-oriented... ...timing and DFT signoff at SOC level.4+... ...in working with physical designers on DFT...SeniorFull timeInternshipLocal areaImmediate startShift workIntel
Santa Clara, CA16 hours ago- ...NVIDIA Corporation is seeking a Senior Physical Design and Timing Engineer to lead high-frequency and low-power design across CPUs, GPUs, LPUs and SoCs. The role emphasizes RTL-to-tapeout, floorplanning, and ECO troubleshooting with cross-functional collaboration across...Senior
$100k
...industry on cutting-edge AI technology,... ...contributors of all seniorities. Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives... ...automation strategy, and signoff infrastructure for high... ...determine where data-driven optimization delivers...Full timeRemote workTenstorrent
Santa Clara, CA15 days ago- ...RoleIntel is seeking a Senior Design Verification Engineer for the Silicon... ...from planning through signoff. You will drive quality... ...breadth in RTL, physical design, and CAD to contribute... ...boundaries. AI-assisted workflows are... ...including ML-driven verification flowsMentor...SeniorFull timeInternshipLocal areaImmediate startShift work
Intel
Santa Clara, CA1 day ago $138k - $206k
...whose innovative designs are pushing the boundaries... ...and growth are driven by an inclusive... ...demands of future AI/ML workloads. Our... ...hardware and software engineers to identify and... ...'ll Do Own the physical implementation of... ...development, and signoff, resolving setup/hold...SeniorWork at officeFlexible hoursNight shift- ...Synopsys, Inc. in Sunnyvale seeks a Senior RTL-to-GDS Engineer to drive physical design from RTL through tapeout using Fusion Compiler and related tools. You... ...will script in TCL/Python to automate workflows, apply AI-assisted methods, and collaborate with customers to...
$138k - $197k
...ASIC’s and SoC’s, from design through manufacturing,... ...and reliability using physical design and circuit techniques... ...s degree in Electrical Engineering, Computer Engineering,... ...to shape the future of AI/ML hardware... ...integration within AI/ML-driven systems.As a Physical Design...WorldwideGoogle
Sunnyvale, CA4 days ago$168k - $264.5k
...loses it. This role co-designs them. The Silicon Co-Design... ...the world's AI infrastructure demands,... ...reason why.You will be the engineer who knows what these circuits... ...analysis, transistor physics, and silicon... ...to its root cause and driven the fix all the way through...SeniorFull timeNvidia
Santa Clara, CA4 days ago- ...Physical Design Engineer - Location: San Jose OR Irvine, CA Our client... ...capable of running AI workloads alongside bandwidth... ...an experienced Senior SoC/ASIC Physical Design... ...tool capabilities and ML‑driven optimizations to... ...verification, EM/IR checks, and signoff tasks. Enhance...Full timeH1bVisa sponsorshipRelocation package
Gyga Force Co
San Jose, CA4 days ago - ...that powers tomorrow’s AI supercomputing. From... ...to scalable photonic engines, Lumilens is unlocking... ...Every line of code, every design decision, every... ...We are seeking a Senior Physical Design Engineer to join... ...placement and routing. # Signoff and Tape out: Perform...Senior
Lumilens
San Jose, CA2 days ago $230k - $400k
...U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62. About The Role Own floorplan‑to‑signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip‑design and software teams driving DensityAI’s AI accelerator program from...Permanent employmentH1bVisa sponsorshipWork visaDensityAI
Mountain View, CA2 days ago$100k
...leading the industry on cutting-edge AI technology, revolutionizing... ...for contributors of all seniorities.Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks... ...early architecture through final signoff.What You Will LearnHow to...Permanent employmentTenstorrent
Santa Clara, CA1 day ago- ...NVIDIA Corporation in Santa Clara, CA, seeks ASIC Design Engineers with experience in agentic AI to design and implement world-leading SoCs and GPUs. Join the AI for chip design team and tap into AI's potential to transform chip design. You will develop RTL in Verilog...Senior
$135.9k - $201.13k
...Across enterprise, cloud and AI, and carrier architectures... ...Team, Your ImpactAs a Senior Staff Digital ASIC Design Engineer at Marvell, you will join... ...speed datapaths, and DSP driven processing engines that enable... ..., verification, physical design, and systems to deliver...SeniorPermanent employmentFull timeInternshipWork from homeMarvell
Santa Clara, CA2 days ago$164.47k - $232.19k
...seeking a Silicon Photonics Design Engineer specializing in actives design... ...innovation in data center and AI applications.About the... ...optical communications and AI-driven systems. Joining IPS means becoming... ...in Electrical Engineering, Physics, Optical Science, or a related...SeniorFull timeLocal areaImmediate startShift workIntel
Santa Clara, CA2 days ago$138k - $197k
...Share Physical Design Engineer, 3D Technology corporate_fare Google place Sunnyvale, CA, USA ~ Bachelor... ..., you’ll work to shape the future of AI/ML hardware acceleration. You will have... ...and its integration within AI/ML-driven systems. As a Physical Design Engineer...Worldwide$100k
...leading the industry on cutting-edge AI technology, revolutionizing... ...looking for contributors of all seniorities. As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on... ...multi-stakeholder projects. - Detail-driven, with a strong sense of ownership...Full timeRemote workTenstorrent
Santa Clara, CA25 days ago- ...Application Engineering Application Engineering Description... ...cloud computing, and AI, we depend on... ...impactful: We're a mission-driven startup,so you'll... ...We are looking for a Senior Design Verification Engineer... ...customer design, and signoff (Logic and DV) Integration...SeniorWork at office
proteanTecs
Santa Clara, CA16 hours ago - ...computing experiences—from AI and data centers, to PCs,... ...beyond. THE ROLE: As a Senior CPU Design Verification Engineer, you will join a CPU... ...methodologies, including AI-driven development and debug, to... ...medical condition, mental or physical disability, national...Senior
Advanced Micro Devices , Inc.
Santa Clara, CA16 hours ago $106.4k - $172.15k
...Integrity, and Inclusion. We weave AI into the fabric of... ...Summary Your Career As a Design Verification engineer on the ASIC team, you will... ...using sophisticated coverage-driven, constrained-random... ...condition, national origin, physical or mental disability, political...SeniorFull timeCasual workWork at officePalo Alto Networks
Santa Clara, CA1 day ago$153.5k - $310.5k
...Senior Design Verification EngineerThis role has been designed... ...seeking a talented and driven Senior Design Verification Engineer with specialized knowledgeand... ...~ Familiarity with AI/ML application and... ...benefits that supports their physical, financial and emotional...SeniorWork experience placementWork at officeLocal areaImmediate start2 days per weekHobbsnews
Sunnyvale, CA16 hours ago$119.85k - $162.15k
...Space and Security is hiring ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) at... ..., top‑level timing closure, signoff readiness, and tapeout activities... ...and lead technical efforts (for senior/lead levels). Occasional travel...SeniorPermanent employmentWork experience placementInterim roleRelocationVisa sponsorshipWork visaFlexible hoursShift workDay shift- ...is the leader in engineering solutions from silicon... ...rapidly innovate AI-powered products.... ...-leading silicon design, IP, simulation and... ...the trenches of physical design, where the... ...know that getting to signoff is not about... ...machine learning-driven design optimization...
$119.85k - $239.2k
ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior) Company: The Boeing Company Boeing Defense, Space and Security is... ...integration, top‑level timing closure, signoff readiness, and tapeout activities....SeniorPermanent employmentFull timeWork experience placementInterim roleRelocationVisa sponsorshipWork visaFlexible hoursShift workDay shift
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Senior Staff Physical Design Engineer: AI-Driven Signoff. Be the first to apply!
Related searches
- software engineer staff Sunnyvale, CA
- technology administrator Sunnyvale, CA
- assistant engineer Sunnyvale, CA
- staff engineer Sunnyvale, CA
- senior staff systems engineer Sunnyvale, CA
- senior staff engineer Sunnyvale, CA
- engineering aide Sunnyvale, CA
- asic digital design engineer Sunnyvale, CA
- senior software design engineer Sunnyvale, CA
- product design engineer Sunnyvale, CA