Design Engineering Architect

Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry. Responsibilities Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals. Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic. Oversee pre-silicon verification activities, including lint, CDC, formal verification, and other quality checks. Work closely with cross-functional teams, including Design Verification, Physical Design, Architecture, and firmware engineers, to ensure successful delivery. Qualifications 10+ years of front end design and/or verification experience, with a BS or MS in Engineering or Computer Sciences. Proven experience in leading and managing complex engineering projects. Rich experience in IP creation and/or SoC and IP (CPU, memory, interface) integration. Expert in RTL design (Verilog), simulators, and debuggers. Hands-on experience in synthesis, SDC creation, and support for PD and STA teams. Experience driving results in a multidisciplinary organization. Desired Qualities A self- motivated person with strong communication and design-management skills. Experience with Cadence front-end toolset. Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, veteran status, disability, or any other protected class. #J-18808-Ljbffr Cadence Design Systems, Inc.