Senior Verification Engineer

Responsibilities:

• Design and implement verification plans.
• Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design.
• Collaborate with the hardware design team to identify and resolve issues.
• Working in a UVM environment.
• Use of Assertions, random testing, functional and code-based coverage.
• Analyze and report on verification results.

Qualifications:

• Bachelor's or Master’s degree in Electrical Engineering, Electronics Engineering or related field.
• At least 7 years of experience in hardware verification.
• Strong knowledge of industry-standard verification tools and methodologies.
• Familiarity with ASIC design.
• Excellent analytical and problem-solving skills.

Strong communication and collaboration skills.

#J-18808-Ljbffr