Senior IP Characterization Engineer

We are seeking an experienced Library Characterization Engineer to support the development and characterization of high-performance, low-power, and ultra-high-density standard cell libraries and hard IPs. The ideal candidate will have strong experience in transistor-level simulations, library characterization flows, design kit generation, and test-chip tapeout activities. This role involves close collaboration with physical design, RTL, and backend CAD teams to ensure high-quality design kit releases and successful program execution. Key Responsibilities Execute characterization flows for high-performance, low-power, and ultra-high-density standard cell libraries and hard IPs. Generate front-end and back-end design kit views for release. Run transistor-level simulations (SPICE), perform custom physical layouts, and manage automated library characterization flows. Collaborate with Physical Design, RTL, and Backend CAD teams to identify and resolve design kit quality issues. Perform high-sigma analysis, including Monte Carlo simulations using PrimeSim DR and High Sigma Analysis (HSA). Perform library quality assurance and cross-checks using tools such as Crosscheck and SolidoChar. Support PPA analysis, engineering benchmarking, and design kit completeness. Contribute to test-chip tapeouts, including end-to-end design ownership and sign-off of individual partitions. Required Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. 6+ years of experience in semiconductor engineering, preferably within a foundry environment, driving PPA analysis and engineering benchmarking. Hands-on experience with characterization flows for IPs, standard cells, and memory compilers. Experience with library characterization and design kit generation tools such as Liberate and Totem. Strong scripting skills in Python, TCL, Perl, or SKILL for automation and large-scale data analysis. Expert-level proficiency with design environments and simulation tools such as Cadence Virtuoso, HSPICE, and Spectre. Proven experience participating in test-chip tapeouts, including ownership of end-to-end design and sign-off of partitions. Working knowledge of synthesis, Place & Route (PnR), Static Timing Analysis (STA), and Physical Design Verification (PDV) tools. Understanding of back-end design kit views and release processes. Preferred Qualifications Experience with PrimeSimDR/HSMC. Familiarity with EDA validation tools such as LEC, Calibre, Totem, PrimeLib, and SolidoIPValidation. Understanding of CMOS device physics, digital circuit design, and advanced-node layout constraints. Experience with high-sigma Monte Carlo simulations and library QA methodologies. Interested? If you have hands-on experience in standard cell characterization, library development, and advanced semiconductor design, we'd love to hear from you. #J-18808-Ljbffr Sintegra Inc.