Staff Design Verification Engineer (SystemVerilog/UVM)
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Analog Devices, Inc. in Chandler, AZ seeks a Staff Engineer in Design Verification to define interfaces, verify state machines, and build metric-driven SystemVerilog/UVM environments for data center, energy, and automotive applications.
You will develop directed and constrained random tests, write Verilog-AMS and Real Number Models, and contribute to product definitions while enjoying a partial telecommute option.
#J-18808-Ljbffr Jobleads-USVacancy posted 15 hours ago
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