Senior Principal CPU Microarchitect

Responsibilities

• Creation of a microarchitectural specification for a major block from early exploration through micro architectural definition in conjunction with the performance modeling team and arriving at a detailed specification RTL design of the major functional block.
• Ownership includes the design definition, implementation and convergence of the block to project requirements (performance, timing, power, area, schedule).
• Support of the verification team for test bench development, test plan development and test content development, including performance verification.
• Work with physical design teams, and design for testability teams to implement and converge physical design and testability.

Requirements

• Minimum BS and 15+ years of relevant industry experience
• Experience with CPU microarchitecture, in at least one of the following areas: instruction fetch, branch prediction, instruction decode, instruction scheduling, out of order execution, register renaming, integer or floating point execution, exception handling, load/store execution, cache design, or memory management unit
• Experience with Verilog, System Verilog, or VHDL
• Experience with commercial simulators and debugging tools
• Expert in logic design