Staff Hardware Engineer, CAD Infrastructure

Staff Hardware Engineer, CAD Infrastructure Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools. The Hardware Engineering group is responsible for all fabric and SoC hardware design at Achronix. It develops custom circuits required to design the FPGA fabric, and designs and integrates high-speed SOC blocks, network-on-chip (NoC), clocking and reset, etc. The Hardware Engineering group is hiring a Staff Engineer, who will be responsible for creating and maintaining the physical design and CAD infrastructure required for physical and custom circuit design. The employee will own the development, testing, and maintenance of physical design verification flows such as DRC, LVS, Fill, etc., download, maintain and install FAB collateral and maintain the CAD infrastructure required for the project, including downloading and installing CAD tools and creating/testing the various flows that use them. The employee may also contribute to methodology development. The employee should be self-driven, constantly looking to set the bar higher, and a driver of excellence. The employee should have a strong background in Tcl and Python/Perl coding. Job Description/Responsibilities The employee’s responsibilities will include the following: Download, install and maintain FAB collateral Create, test and maintain physical design verification flows such as LVS, DRC, Density, Fill, Antenna, etc. Be able to work with data management and revision control systems such as Perforce. Download, maintain and test CAD tools required for custom layout (e.g. Custom Compiler), Physical Design (e.g. Fusion Compiler), ICV, RedHawk, Totem, Hspice, etc. Contribute to methodologies and best practices across all custom and ASIC physical design Skills Experience with physical verification (DRC, LVS, Fill, Density, Antenna, etc) Experience working with physical design tools and flows Excellent working knowledge of Python, knowledge of scripting tools such as TCL, Perl, etc Excellent grasp of data management and revision control systems such as Perforce Excellent working knowledge of physical design collateral needed from FAB vendors and CAD tool vendors from GDS to tapeout Some experience with synthesis and physical design (RTL2GDSII) a plus Excellent written and verbal communication skills Intrinsically driven, and always raising the bar Ability to take high-level requirements, and create solutions around those. Must be able to see the big picture Thrives in a dynamic and fast-paced environment, with a pro-active mindset Works well with other team members and has a collaborative approach Education and Experience BS or MS and 6+ years of experience Previous experience in at least two product developments #J-18808-Ljbffr Achronix Semiconductor Corporation