Design Verification Engineer

Design Verification Engineer Broadcom's ASIC Products Division (APD) is looking for an experienced verification engineer responsible for modeling and verification activities for complex digital and mixed-signal (MXS) IP blocks used in Broadcom’s ASIC developments. Responsibilities Define verification plans and environment architecture. Develop test cases and test bench components, coverage analysis and closure, and debug. Work with emulation and FPGA prototyping platforms, evaluate and drive adoption of advanced verification methodologies/flows. Develop functional models to facilitate block, system, and ASIC level verification. Collaborate closely with design teams and EDA vendors. Analyze and debug simulation failures at RTL and gate-level. Ensure knowledge of RTL, gate-level netlists, SDF, and debug such formats. Qualifications 6+ years of experience with verification concepts and architectures for complex digital and MXS circuits. Experience verifying designs at block and system levels. Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC). Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits. Experience using SystemVerilog and UVM, designing verification components including agents, checkers, and behavioral models. Experience with random & directed test cases, SystemVerilog Assertions. Experience with Synopsys, Cadence, and Mentor simulation tools. Demonstrated ability to plan and deploy complex, reusable, scalable verification environments. Experience with Perl/Python and Tcl or other scripting languages. Experience with version control systems (DesignSync, git). Superior writing, grammar, and verbal communication skills. Excellent problem solver; develops and employs automated processes where applicable. Worked independently and as part of a global team in a highly visible role. Ability to learn and adapt to new tools and methodologies on the fly. Must have legal authorization to work in the US. Preferred Experience Hardware design and debug. Emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms. Formal verification concepts/experience. Verifying iJTAG network using ICL and PDL in the Tessent tool. Co-simulation. Education & Experience BS in Electrical Engineering / Computer Engineering and 8+ years of related experience. MS in Electrical Engineering / Computer Engineering and 6+ years of related experience. Compensation and Benefits The annual base salary range is $108,000 - $172,800. Eligible for a discretionary annual bonus, new‑hire equity grant, and annual equity awards. Benefits include medical, dental and vision plans, 401(K) participation with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Equal Opportunity Employer Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. #J-18808-Ljbffr