Design Verification Engineer

Job ID: SRJ_7188Posted: Location: Sunnyvale , CA; Redmond , CA; Austin , CASalary: USD 100-135 / Yearly (Full Time)Employment Type: Full TimeIndustry: Computer SoftwareClient: WiproContact: Meghana GorusuCompany: SRI Tech SolutionsJob Title:Design Verification EngineerLcation: Sunnyvale CA /Redmond WA/ Austin TX Onsite (Hybrid) Role
NO Remote AllowedKey Responsibilities:NO 18+ yrs profilesNo Contractors-IP level Verification
- SOC Design Verification· Strong understanding of SV and UVM and good debugging skills.· Understanding of AMBA protocols.· Understand design specs and developtest plansbased on functional and architectural requirements· BuildUVM/System Verilog-based verification environmentsfor IP/subsystem/SoC level testing· Develop directed and randomtestcases, perform coverage analysis, and close functional/code coverage· Debug simulation failures andwork closely with RTL designersto resolve issues· Executeregression runs, analyze results, and contribute to continuousimprovements· Integrate and runpower-aware simulations,low power checks, and work with UPF/CPF as needed· Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains· Document test environments, test plans, and results for internal and external reviewsSRI Tech Solutions is an equal opportunity employer and does not discriminate on the basis of race, color, gender, religion, age, sexual orientation, national origin or citizenship status or ethnic origin, disability, marital status, veteran status, or any other occupationally irrelevant criteria.