FPGA Engineer

FPGA Engineer Overview Develop FPGA designs including: Xilinx, Altera,and Microsemi. Designs are implemented using VHDL Applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required. Responsibilities Design and deliver production quality FPGA releases from initial proof of concept up to production Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS) Translate system level requirements into FPGA requirements Design and code in VHDL for reliability and maintainability Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage Help drive projects and execute to program schedules on time and budget Create complete documentation including requirements, verification plan, and user’s guides Qualifications Bachelor of Science in Computer or Electrical Engineering 2-8years+ of experience to include the following: FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) Xilinx or Microsemi devices and flow tools Delivering FPGA/ASIC solutions to system level applications Hands on experience with integration and debug of FPGA/ASIC devices A US security clearance Pluses Preferred Experience FPGA design experience in one or more of the following areas: Radar processing techniques Image processing techniques for visual and infrared sensors Embedded systems design using ARM, Microblaze, or Nios processors Gigabit serial interfaces and multi-gigabit transceivers (MGTs) Constrained random verification in UVM using System Verilog Verification utilizing emulation platforms, such as Veloce #CJ #J-18808-Ljbffr