ASIC/FPGA Verification Engineer - UVM Expert
New York Life Insurance
New York Life Insurance in Seattle seeks an Associate ASIC-FPGA Verification Engineer to support multiple product lines in commercial and defense electronics development. You will use architectural docs to implement test bench functions, develop SystemVerilog models, and create scripts and Makefiles for verification work. The ideal candidate has 6–9 years of digital ASIC/FPGA verification, deep UVM knowledge, and proven experience building self-checking test benches for SoCs/FPGA. #J-18808-Ljbffr New York Life Insurance
Vacancy posted 1 day ago
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