Lead VCS Verification Engineer (UVM, Debug & Deployment)
Synopsys
Synopsys Inc. is seeking an experienced Verification Engineer in Austin to lead VCS deployments and work closely with design and verification teams to integrate cutting-edge simulation tooling into their flows.
You will diagnose complex issues, optimize performance, and translate customer feedback into actionable product requirements. You will leverage SystemVerilog, UVM, SVA, Verilog and VHDL to debug and validate testbenches, and collaborate with R&D on improvements.
#J-18808-LjbffrVacancy posted 2 days ago
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