Principal Model Researcher

Principal AI Model Architect – Silicon-Software Co‑Design Austin, Texas We need a Principal AI Model Architect to work at the intersection of machine learning research and silicon design. You will shape hardware around state‑of‑the‑art transformer architectures and guide the translation of model specifications into silicon‑level designs. Responsibilities

• Own the hardware‑software bridge – translate AI and RAN algorithms (e.g., Transformers, Grouped Query Attention, Rotary Positional Embeddings) into precise hardware specifications for the ASIC team and concrete lowering requirements for the SDK team.
• Define model partitioning and tiling strategies for multi‑hundred‑million‑parameter models across heterogeneous compute fabrics, including tensor parallelism, pipeline stages, and memory tiling across HBM and on‑chip SRAM.
• Maintain the canonical reference implementations in JAX and PyTorch, ensuring the “Source of Truth” for the entire program and verifying that silicon execution matches the intended model behavior.
• Project performance before RTL is written, using cycle‑accurate simulators, SystemC models, and deep intuition to provide the silicon team confidence for tape‑out decisions.

Qualifications

• Deep knowledge of Transformer architectures, including how design choices (attention head count, KV‑cache sizing, embeddings, GQA vs. MQA) affect hardware execution profiles.
• Hardware‑aware machine learning experience: understanding cache line interactions, memory bandwidth bottlenecks between HBM and SRAM, and how SIMD/VLIW execution units affect model shapes.
• Advanced proficiency in JAX (strongly preferred), PyTorch, or TensorFlow at the export and compilation layer, with experience in graph capture, XLA, and StableHLO.
• Experience with SystemC, transaction‑level modeling, or custom cycle‑accurate simulation frameworks for validating architectural decisions.

Preferred Expertise

• Telecommunications background: applied AI to RAN workloads such as channel estimation, beamforming, and interference management at L1–L3.
• Compiler curiosity: intuitive understanding of the journey from high‑level compute graphs to hardware‑bound execution sequences.
• Numeric sensitivity: hands‑on experience with complex‑valued AI models and the challenges of mapping to DSP or matrix accelerator hardware, including fixed‑point quantization and dynamic range considerations.

Why This Role Is Different This role bridges research and silicon at an unprecedented depth. It requires someone who can operate at the intersection of cutting‑edge transformer models, compiler logic, and silicon design, making decisions that shape both software and hardware. Benefits

• Competitive compensation based on location, experience, and education.
• Comprehensive health benefits, including three medical plan options and a dental plan.
• 401(k) plan with company match and stock purchase plan participation.
• Generous paid time off, vacation, holidays, and parental leave.
• Additional benefits: financial wellness programs, educational assistance, matching gifts, and recognition programs.

Equal Opportunity Ericsson is an Equal Opportunity employer and encourages people from all backgrounds to apply. #J-18808-Ljbffr Ericsson