Senior Physical Design Methodology Engineer, Innovus Flows
$168k - $264.5kNVIDIA
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA's products – Datacenter AI, HPC, Networking, Robotics, Autonomous driving, gaming and more. As the cadence of NVIDIA’s chip cycle shortens, it poses new challenges for physical design teams to not only deliver the best PPA on the chips, but to also do it at scale, in the shortest possible time. Your work in physical design methodology directly enables our speed to market in delivering industry’s leading chip hardware. This role provides a unique opportunity to innovate at the cutting edge of process technology, EDA tools, and PD flows through collaboration with RTL, synthesis, DFT, foundry, timing other cross functional teams to push the limits of physical design at scale.What you'll be doing:Developing innovative physical design methodologies for implementation of GPU, CPU, Network processors and SOC, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodesWork with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product linesUse AI/ML approaches to CAD to improve design performance and turnaround time, while improving efficiency and productivity of designersWhat we need to see:MS in Electrical or Computer Engineering (or equivalent experience)Minimum 7 years of experience in Physical Design; emphasis on methodology and flow development is highly preferredProven track record of PPA improvement on high performance and low power designs in advanced technology nodesStrong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimizationStrong background in STA, extraction, timing and RC correlationExperience in low power design with UPF, and use of FSDB/SAIFs for power optimizationSolid understanding of EM and IR analysis and closureUnderstanding of synthesis, hierarchical design, pinning and budgeting flowsExperience with power distribution networks, Design for Yield and Manufacturability and thermal managementExpertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++Ways to stand out from the crowd:Experience applying ML models, LLMs, and agentic AI techniques to EDA/PD problems (analytics, prediction, optimization)Proficiency with data analysis/ML libraries (e.g., NumPy, SciPy, scikit-learn, PyTorch, etc.)Proficiency in Cadence EDA tool suite – Innovus/genus/tempus/quantus/joules etc.NVIDIA is widely considered to be one of the technology world’s most desirable employers. And due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until September 6, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa Clara; US, TX, Austin; US, TX, Remote; US, CA, RemoteType: Full time
$168k - $264.5k
...Doing Developing innovative physical design methodologies for implementation of GPU,... ...of the physical design flow on advanced technology nodes... ...in Electrical or Computer Engineering (or equivalent experience)... ...Cadence EDA tool suite - Innovus/genus/tempus/quantus/...Senior$168k - $264.5k
We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over... ...in establishing physical design methodologies, flow automation, chip floorplan, power/clock... ...(ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor...SeniorFull time- NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next...SeniorFull time
$168k - $264.5k
...work. Come join the team and see how you can make a lasting impact on the world.NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Improvement Technology Scaling to join our outstanding Methodology team. Come and take a part in...SeniorFull time$100k
...contributors of all seniorities.Our IP delivery... ...are set as much by flow maturity as by design work. This role develops... ...the RTL-to-GDSII methodology the IP physical design team runs... ...CAD methodology engineer who has built... ...FusionCompiler/ICC2, Innovus/Genus, PrimeTime,...SuggestedPermanent employment$168k - $264.5k
...current EDA. NVIDIA's interposer designs are among the most complex... ...small group of high-impact engineers who define how that design... ...requires you to build flows and methodologies that automates interposer design... ...with interposer and IC physical design.Strong expertise in...SeniorFull time$128.6k - $217.2k
Senior Physical Design EngineerCategoryChip DesignLocationAustin, TXExperienceMore than 8 Years... ...seeking a Senior Physical Design Engineer to drive Advanced Place & Route (APR... ...issues.Support and enhance design methodologies and flows to improve quality, scalability, and...SeniorTemporary workWork at officeWork from home$184.7k - $324.8k
...product!Come help us design the next generation of... ...and unusually talented engineer. As a member of our dynamic... ...craft and implement methodologies with a high impact on... ...involved in our physical design methodology efforts... ...by running our signoff flows and comparing results...Relocation$214.1k - $309.8k
...product development—from design to qualification to... ...• Analyze existing tool flows and methodologies, identifying efficiency... ...’s Degree in Electrical Engineering with 12+ years of Physical Design experience or Master... ...working with EDA tools like Innovus, Primetime/Tempus,...SeniorFull timeTemporary workLocal areaFlexible hours$183k - $247.6k
...Acceleration (MLA) team designs and develops the SOCs that... ...worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a... ...project by automating design flows and building large-scale... ...implementation, synthesis, STA and physical design in deep sub-micron...SeniorLocal areaWorldwideFlexible hours- Highbrow Technology Inc is seeking an experienced ASIC Physical Design Engineer to execute synthesis, PnR, and timing for... ...issues, driving EM/IR closeouts and signoffs with methodology owners. Proficiency in all PnR flows and EDA tools will be essential. #J-18808-Ljbffr...Senior
- Etched.ai, Inc. is seeking a Physical Design Engineer based in Austin, Texas. This role involves owning block-level implementation, driving timing closure, and collaborating with RTL designers to improve design processes. Candidates should have 5-10+ years in physical...SeniorWork at office
$150.4k - $277.6k
...Technologies group, you’ll help design and manufacture our next-... ...SOC designs by developing flows, tools and methodologies for future Apple products!... ...looking for passionate engineers to join our team. In this... ...teams to tackle key physical design challenges.- Developing...Relocation$184.7k - $324.8k
...Technologies group, you’ll help design and manufacture our next-... ...SOC designs by developing flows, tools and methodologies for future Apple products!... ...looking for passionate engineers to join our team. In this... ...teams to tackle key physical design challenges.- Developing...Relocation$100k
...looking for contributors of all seniorities.Tenstorrent is seeking an Physical Design Engineer to lead cross-functional... ...develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong... ...into production physical design flows, creating custom CAD tools and...Permanent employment- ...future. Whether you’re designing next-gen processors,... ...-class hardware physical design flow in a fast-paced production... ...for solving complex engineering challenges and... ...standard EDA tools and methodologies across multiple... ...Fusion Compiler, Cadence Innovus, and PrimeTime....SeniorWorldwide
$115.6k - $173.4k
...DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical... ...requires strong expertise in physical design flow, tapeout readiness, and Power,... ...expertise with: Place & Route tools: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler...SeniorWork experience placement$156k - $229k
Senior CPU Physical Design Engineer, Silicon Base pay range $156,000.00/yr - $229,000.00/yr Minimum qualifications... ...of experience with physical design flow such as constraints, synthesis,... .... Develop physical design methodologies using industry standard EDA tools and...SeniorFull timeWorldwide$239.6k - $324.1k
Annapurna Labs, designs custom silicon powering... ...’re looking for a Senior Manager, Physical Design Engineering to build and lead a... ...architecture, hierarchical methodology, PPA target-setting... ..., reference flow development, PPA... ...RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus,...SeniorLocal areaFlexible hours- ...Electronics (eInfochips) is seeking a Physcial Design Engineer to execute synthesis, PNR, and STA for... .... The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and strong TCL scripting for custom flows on CAD tools. On-site at customer...Senior
$136k - $218.5k
...inventiveness and intelligence.We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you... ...block or full-chip level, at project execution and/or flow development.Strong experience in full-chip/sub-chip...SeniorFull timeShift work$185.2k - $250k
...• Work with RTL/logic designers to drive architectural feasibility... ...-area tradeoffs for physical design closure • Drive... ...Develop physical design methodologies while embracing AI flow • Evaluate 3rd party IP... ...with other physical design engineers as well as with the RTL/...SeniorPermanent employmentFlexible hours- ...propelled by the top engineers in mixed-signal processing... ...for an expert Physical Design Engineer to join its... ...automating and advancing flows using proficiency in... ...familiar with Cadence Genus/Innovus and Synopsys Design... ...physical design methodologies and flow automation.Ability...Full timeWork at officeRelocation
- ...-14SummaryWe're seeking a Physical Design Signoff Engineer to join our team and drive... ...open items, and alignment of methodology across groups. We are... ...infrastructure, and performing flow signoff to verify that CAD... ...tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler...
- ...enabling human life on Mars.SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’re... ...)Develop/improve physical design methodologies and automation scripts for various implementation... ...design/timing/congestion and flow issues, identify potential solutions...SeniorPermanent employmentWorldwideWeekend work
$183k - $247.6k
Annapurna Labs designs silicon and software that accelerates innovation... ...We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new... ...- Develop physical design methodologies- Evaluate 3rd party IP and... ..., or Others) develop flows for synthesis, formal verification...SeniorLocal areaFlexible hours$100k
...contributors of all seniorities.Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff... ...verification flows.A collaborative team... ..., ICV, Pegasus, FC, Innovus, etc.).Strong background... ...verification methodologies and flow optimization...Permanent employment$186.7k - $280.1k
...Technologies, Inc.Job Area:Engineering Group,... ...world to create designs that push the envelope... ...Cores. As a CPU Physical Design Timing... ...industry standard tools/flows. One of your... ...infrastructure and methodology impacting... ...RTL to GDS : ICC, Innovus , PT/TempusMinimum...Work experience placementWork from home$164k - $246k
...Job Area Engineering Group, Engineering... ...Responsibilities Update the physical implementation flows for optimum PPA... ...of semi-custom design techniques where... .../enhance design methodologies to achieve the... ...is consulted by senior leadership to... ...Cadence Genus, Innovus) ~ Very good...Work experience placement$174.4k - $261.6k
...Inc. Job Area: Engineering Group, Engineering Group... ...: QCT’s NSP Physical Design Team is actively seeking... ...mesh, and clock spine methodologies. This role... ...ICC2 and/or Cadence Innovus Synopsys PrimeTime... ...and DRC/LVS signoff flows Strong understanding...SeniorWork experience placementWork from home
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