Senior ASIC Architect & Tech Leader, Hyperscale Connectivity (San Jose)

Astera Labs is looking for a Distinguished Engineer in San Jose, CA to lead the architecture of high-speed connectivity silicon for AI systems. This role involves defining system and chip architecture across PCIe and Ethernet-based subsystems, ensuring performance and cost efficiency.

The successful candidate will have extensive experience in semiconductor architecture and be involved in technical mentorship. The position offers a unique opportunity to impact next-gen AI infrastructure.