Senior ML Accelerator DV Engineer
Amazon Locker
Amazon’s Machine Learning Acceleration team in Cupertino seeks a skilled Design Verification Engineer to verify SOCs for Inferentia and Trainium, collaborating across teams to optimize silicon yield and performance. You will contribute to testbenches, coverage plans, and robust debugging in a high-throughput data center environment. The role requires strong SystemVerilog/UVM expertise, hands-on testbench development, and experience with C/C++ and Python. #J-18808-Ljbffr
Vacancy posted 3 days ago
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