Hybrid Senior ASIC Verification Engineer
Hewlett Packard Enterprise
Hewlett Packard Enterprise invites a Senior ASIC Verification Engineer to join our dynamic team in Sunnyvale, CA on a hybrid schedule requiring ~2 days in office weekly. You will design, verify and validate VLSI blocks, build test benches in SystemVerilog/UVM, and collaborate with logic and software teams to deliver robust chips and platforms. This role offers opportunities to influence product architectures and advance your expertise in cutting‑edge verification techniques. #J-18808-Ljbffr Hewlett Packard Enterprise Company
Vacancy posted 5 days ago
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