Senior Analog Design Engineer

Job Description The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry-defining analog and mixed-signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die‑to‑die interfaces across multiple advanced process nodes. We are seeking an experienced Senior Analog Design Engineer to join our engineering team. The successful candidate will design, develop, and optimize analog and mixed‑signal integrated circuits for various applications and lead complex projects from concept to production. Key Responsibilities Design and Development Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks. Develop circuit architectures and perform detailed transistor‑level design. Create and optimize layouts working closely with layout engineers. Perform circuit analysis, simulation, and verification using industry-standard tools (Cadence, Synopsys, etc.) and leverage automation and AI-supported solutions. Technical Leadership Lead analog design projects from specification to silicon validation. Mentor junior engineers and provide technical guidance. Collaborate with cross‑functional teams including architecture, logic, verification, physical design, layout, post‑silicon manufacturing, validation teams, and SOC partners. Drive design reviews and ensure adherence to design methodologies. Facilitate design development and convergence across global teams designing concurrently in numerous process nodes, working with teams in the US and India. Validation and Optimization Develop test plans and oversee silicon characterization. Debug and resolve design issues during pre‑ and post‑silicon phases. Optimize designs for performance, power, and area requirements. Ensure designs meet specifications and industry standards. Candidate Profile Good communication and documentation skills, with a collaborative and proactive work style. Demonstrated ability to work effectively in cross‑functional, global teams and contribute to technical reviews. Strong analytical thinking, hands‑on debugging skills, and an eagerness to learn and share expertise within the team. In this role, you will drive the definition, design, and verification of high-performance analog blocks, IP top-level designs, and subsystems (floor planning, power delivery, bump maps), collaborating closely with system architects, logic designers, and layout engineers. You will facilitate technical discussions, hold design reviews, and play an active role in post‑silicon validation and performance optimization. The position involves providing guidance to layout engineers and mentoring junior analog designers as needed. Strong problem-solving skills, teamwork, and a willingness to share knowledge are essential. This role offers an opportunity to develop innovative designs and be part of a highly experienced IO and die‑to‑die design team focused on delivering next‑generation high-speed interconnect solutions. This is an on-site role and you are expected to work in the office at least 4 days per week. Qualifications Minimum Qualifications Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. 6+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications. Your Experience Must Include Proven experience in one or more of PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter (TX), Power Delivery design, IP floor planning, IP top-level performance simulation, signal integrity analysis. High-speed IO calibration and training algorithms. High-speed communication standards such as UCIE and PCIe (Gen5/Gen6/Gen7). Core analog design principles, including noise, linearity, matching, and stability. Hands‑on experience with advanced FinFET CMOS process technologies. Analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent. Post-silicon validation, lab measurements, and debugging of analog circuits. Preferred Qualifications Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline. 7+ years of experience in analog design for high-speed SerDes and/or die‑to‑die applications. In-depth understanding of transmitter and receiver design, CDR loops, and equalization techniques. Exposure to next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD. Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl). Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis. Background in standard and advanced package technologies. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, Arizona, Phoenix Additional Locations US, Oregon, Hillsboro Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $190,610.00 - 269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr Intel