Senior Principal Compiler Engineer - SV for AI NPUs
Cadence Inc
Cadence is seeking a Senior Engineer in the System Verification Group to develop the next generation of hardware verification technology. This role focuses on evolving the SystemVerilog compiler to handle the complexities of AI and hyperscale chip designs. The successful candidate will work on compiler architecture and language evolution while undertaking performance engineering to optimize compilation speed. The position offers significant impact in the semiconductor industry and a competitive salary range. #J-18808-Ljbffr Cadence Inc
Vacancy posted 1 day ago
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