Integration and Metrology Engineer (50736)
$121k - $160kHeadway Technologies
SUMMARY Under the direction of the Sr. Manager, Plating Manufacturing Engineer, the Integration and Metrology Engineer is responsible for monitoring, sustaining, and providing support for the manufacturing process. This includes detecting and correcting process errors; releasing and integrating new programs into the manufacturing line; providing guidance and support to engineers regarding experiments or evaluations; and providing feedback to the back‑end process group. The engineer creates recipes and develops methodologies to improve wafer quality on prototype wafers, focusing on detecting and characterizing wafer‑level visual defects using Focused Ion Beam (FIB) and Automatic Inspection Tool (AIT). ESSENTIAL FUNCTIONS Engages in process improvement activities based on Wafer Design Change Notifications (WDCN) and Wafer Process Change Notifications (WPCN), including following up with CCN documentation for line conversion activity Examines newly transferred products to ensure leading wafer follows wafer configuration specifications Creates and optimizes recipes for both FIB and automatic inspection tools Interacts and responds to inquiries from other engineering groups regarding new metrology requests, wafer quality, or yield issues Improves wafer‑level defect and yield by conducting comprehensive failure analysis using FIB, AIT, and microscope and provides detailed analysis Drives failure analysis, presents findings, and recommends improvement plans Analyzes data using JMP, MS Visual Basic, or similar software application to determine root cause of process variations; develops charts or reports and presents findings Evaluates sample wafers, conducts experiments, and reviews results in support of yield improvement activities; issues Lot Configuration Changes (LCC) and CCN’s as needed Interprets analytical defect data from imaging equipment such as FIB, SEM, EDX, and TEM Monitors and supports manufacturing process controls to alert for abnormal wafers; recommends corrective action if needed Responds to inquiries from other team members, managers, or departments Uses Statistical Process Control (SPC) and other complex software applications to analyze large volumes of data; develops charts or reports and presents findings before groups or teams Adheres to all safety policies and procedures as required Performs other duties of a similar nature or level MINIMUM QUALIFICATIONS Master’s degree in Electrical Engineering, Materials Science, or Physics and/or equivalent relevant experience; PhD preferred Three years of hands‑on experience working in either the magnetic thin film fabrication or semiconductor industries in a manufacturing or process engineering role Strong analytical and critical thinking skills Hands‑on experience in SPC and Design of Experiments (DOE) Proficient in Microsoft Office Applications Knowledge of magnetic recording head or HDD manufacturing Knowledge and ability to understand various defect image results from FIB, SEM, EDX, and TEM tools Knowledge and technical understanding of circuit design and testing Knowledge and experience using JMP or Excel and the ability to create macro formulas Knowledge and ability to use Microsoft Office applications to create spreadsheets, Word documents, and presentations Able to design complex experiments, analyze results, and recommend corrective action Able to communicate effectively, verbally and in writing, with all levels of contractors, consultants, employees, and management Able to work productively and collaboratively with all levels of employees and management Able to comply with all safety policies and procedures Able to use critical thinking to resolve issues, examine trends, conduct root cause analysis, and make recommendations for process improvements Demonstrated analytical, organizational, time‑management, problem‑solving and troubleshooting skills Flexible and able to prioritize SALARY The annual base salary for this full‑time position is between $121,000.00 and $160,000.00 plus bonus target and benefits. The pay may vary depending on additional factors including job responsibilities, related knowledge, skills, abilities, education, and experience. WORKING CONDITIONS The Integration and Metrology Engineer works primarily in an office environment from Monday through Friday. The schedule may change to meet business or operational needs and may involve travel between buildings. The engineer works in a class 100 ESD‑sensitive wafer manufacturing facility and must wear a cleanroom suit, including hood, gloves, safety glasses, booties, and mask. Exposure to hazardous chemicals, fumes, gases, and loud noise is possible. The engineer must be able to stand, walk, bend, twist, perform fine grasping movements, operate a computer, use a keyboard, telephone, and other office equipment, and may occasionally need to push, pull, or lift up to 30 pounds. Other duties of a similar nature or level are duties that may be required but may not be specifically listed in this description. EEO STATEMENT TDK/Headway Technologies, Inc. provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, gender, national origin, age, disability, or genetics. Applicants requiring accommodation to complete the application process should contact the Headway Human Resources Department. #J-18808-Ljbffr Headway Technologies
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