Digital SoC Design Engineer - Wireless Solutions

Digital SoC Design Engineer – Wireless Solutions

Read the overview of this opportunity to understand what skills, including and relevant soft skills and software package proficiencies, are required.

Location: Chandler, AZ

Salary: $145,000 annually + Performance-Based Bonuses

Benefits: Excellent Comprehensive Benefits Package

Travel: Up to 25%

We are seeking an experienced Senior Digital SoC Design Engineer to contribute to the development of next-generation, high-performance, low-power wireless semiconductor solutions. This position focuses on digital System-on-Chip (SoC) design, RTL development, and ASIC implementation.

The ideal candidate will bring extensive technical expertise, strong problem-solving skills, and the ability to collaborate with cross-functional engineering teams throughout the product development lifecycle.

Key Responsibilities

• Design and develop digital SoC solutions from initial architecture through tape-out.
• Perform RTL development using Verilog/SystemVerilog, synthesis, timing analysis, and design optimization.
• Execute ASIC design flows to meet functional, performance, power, and qualification requirements.
• Collaborate with verification, physical design, analog, software, and validation engineering teams.
• Support silicon validation, debugging, and product qualification activities.
• Develop and optimize low-power design techniques and power estimation methodologies.
• Participate in technical design reviews to ensure compliance with engineering specifications.
• Coordinate with external IP providers and global engineering teams to resolve technical challenges.
• Support integration and implementation activities across multiple engineering disciplines.
  

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Minimum 12 years of experience in digital SoC/ASIC design, with a strong emphasis on low-power applications.
• Proficiency in RTL design using Verilog/SystemVerilog, synthesis, SDC timing constraints, and timing analysis.
• Experience with ASIC design methodologies, including LINT, formal verification, CDC/RDC, MBIST/DFT, and power estimation.
• Strong understanding of ARM/MIPS architectures, AMBA/AXI bus protocols, and peripheral interfaces such as USB, Ethernet, I2C, and SPI.
• Experience with bus matrix architecture and design.
• Proficiency in scripting languages such as TCL, Perl, or Python.
• Excellent analytical, troubleshooting, communication, and problem-solving skills.
• Ability to work effectively with multidisciplinary and international engineering teams.
  

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Knowledge of wireless communication technologies, including Bluetooth, BLE, and Wi-Fi.
• Familiarity with hardware security principles and functional safety design requirements.
• Experience with UVM/OVM verification methodologies.
• Hands-on experience with FPGA prototyping, silicon validation, and board-level debugging. xhyhwjd
  

Equal Opportunity Employer

Top Workforce Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected by applicable law.