ASIC RTL Design Engineer - Memory PHY (Hybrid, MA)
Dexian
Dexian is seeking an ASIC RTL Design Engineer specializing in Memory PHY for a hybrid role in Boxborough, MA. The contract is 12+ months, with duties centered on ASIC digital design, Verilog/SystemVerilog RTL coding, and memory interface work. The position supports DDR/LPDDR memory interfaces, high-speed design, and scripting with Python/TCL. Dexian emphasizes equal opportunity employment and global staffing expertise. #J-18808-Ljbffr Dexian
Vacancy posted 3 days ago
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