Integration Engineer or Senior Integration Engineer, Texas Institute for Electronics
Phase2 Technology
Job Posting Title: Integration Engineer or Senior Integration Engineer, Texas Institute for Electronics Position Details Hiring Department: Texas Institute for Electronics Location: PICKLE RESEARCH CAMPUS Weekly Scheduled Hours: 40 FLSA Status: To Be Determined at Offer Earliest Start Date: Ongoing Position Duration: Expected to Continue Purpose The Integration Engineer or Senior Integration Engineer will focus on processing of test and demonstration vehicles in advanced heterogeneous integration projects. Initially responsible for toolset installation and qualification, the role will evolve into establishing best known method flows, characterizing performance, and executing improvements to enhance yield and reliability. Responsibilities Drive unit process engineers and tool/material vendors toward achieving defined targets for integrated test vehicles. Develop successful short‑loop and full integrated processes to demonstrate various heterogeneous integration prototypes. Perform significant hands‑on work within the cleanroom, initially sharing ownership of critical unit processes. Define process windows and resolve excursions through structured troubleshooting and investigation of failure modes. Design and evaluate experiments on test vehicles for mechanical/electrical performance and reliability. Work effectively in a team environment, mentor junior engineers/students, and communicate clearly. Integration Engineer Qualifications Bachelor's degree in semiconductor engineering fields such as Electrical Engineering, Chemical Engineering, Materials Science or other relevant disciplines. Five years of relevant experience, including experience with Cu BEOL interconnects and copper DD unit processes. Experience in W2W or D2WHB preferred. Senior Integration Engineer Qualifications Master's degree or Doctoral degree in semiconductor engineering fields such as Electrical Engineering, Chemical Engineering, Materials Science or other relevant disciplines. Three years of experience in semiconductor process engineering. Experience in W2W or D2WHB preferred. Shared Qualifications Working knowledge or experience with 3D ICs and various integration schemes. Extensive familiarity with standard inline metrology and failure analysis techniques. Experience with test vehicles to establish baseline processes. Ability to work in a cleanroom for extended periods, including gowning to applicable clean‑room standards. Experience with analysis and interpretation of BEOL parametric etest and reliability. Strong data analytical skills (JMP, Python, etc.) and communication skills. Preferred Qualifications Three or more years of experience with unit processes in Copper CMP, particle‑free wet cleans, or bonding. Ten or more years of experience in semiconductor process engineering. Experience in a startup or research and development (R&D) environment. Experience with advanced technology nodes. Experience in test vehicle design, layout, and/or extraction of parametric results. Salary Range TIE Pays Industry Competitive Salaries Working Conditions Work is performed on‑site in a scientific research environment with dynamic work conditions and frequent interruptions. Work is performed in a cleanroom environment, requiring the ability to gown to ISO Class 5 Clean Room standards. Work outside standard office hours may be required on an occasional basis during peak periods and special events. Required Materials Resume/CV Three work references with contact information; at least one reference should be from a supervisor. Letter of interest Equal Opportunity Employer The University of Texas at Austin, as an equal opportunity/affirmative action employer, complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion, or veteran status in employment, educational programs and activities, and admissions. #J-18808-Ljbffr
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