AMD Test Engineer (Infrastructure / High-Speed I/O Specialty)

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whatever you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE AMD is seeking an experienced Test Engineer to develop and advance wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8. In this highly visible role, you will contribute to AMD’s common Base Test Program and Test Shell while leading test enablement for high-speed I/O and die-to-die interfaces. You will have the opportunity to influence test strategy across the full product lifecycle—from first-silicon bring-up and characterization through production release and high-volume manufacturing. Your work will directly improve test quality, yield, test time, scalability, and release readiness for next-generation microprocessor and chiplet products. THE PERSON You are a hands-on ATE Test Engineer with deep experience developing and debugging test programs on Advantest V93000 platforms. You understand how silicon, test software, tester and probe hardware, patterns, timing, and manufacturing processes interact. You bring strong technical judgment, disciplined software-development practices, and the ability to lead complex debug efforts across global teams. You are an effective communicator and mentor who can influence infrastructure strategy across products and organizations. Key Responsibilities Develop and integrate reusable wafer-sort Base Test Program and common Test Shell infrastructure, including test flows, services, configurations, diagnostics, data collection, and release controls. Lead SmarTest 8 and Advantest V93000 test program development, debug, validation, release readiness, and production support. Drive wafer-sort strategy, first-silicon bring-up, characterization, margining, screening, diagnostics, and failure isolation for high-speed I/O and die-to-die interfaces. Integrate patterns, timing, levels, test methods, device configurations, binning, and debug capabilities into the common test program. Troubleshoot complex interactions across silicon, test software, tester and probe hardware, patterns, timing, and manufacturing processes. Partner with Design, Design for Test, Product Engineering, Yield Engineering, Test Hardware, and Manufacturing teams to improve coverage, testability, yield, test time, and product quality. Define scalable architecture and coding practices that enable reuse across products, silicon revisions, test insertions, and manufacturing sites. Lead technical reviews, document architectural decisions, mentor engineers, and support global engineering teams, manufacturing partners, and equipment vendors. Preferred Experience Extensive Advantest V93000 test program development and debug experience, including SmarTest 8. Proficiency in Java and at least one additional language, such as C++, Python, Perl, or shell scripting. Experience developing test flows, methods, patterns, timing, levels, diagnostics, characterization plans, and manufacturing screens. Experience leading or making significant architectural contributions to a Base Test Program, common Test Shell, or similar shared ATE infrastructure. Linux or Unix proficiency, including revision control and disciplined software-release practices. Experience with ORE or comparable offline simulation tools. Experience validating and debugging high-speed SerDes, source-synchronous, memory, or die-to-die interfaces. Knowledge of technologies such as PCIe, CXL, UCIe, Ethernet, JESD204, USB, DDR, HBM PHY, xGMI/Infinity Fabric, UPI, or NVLink. Experience with link training, equalization, lane-level diagnostics, bit-error-rate testing, jitter analysis, voltage and timing margining, or ATE-to-bench correlation. Knowledge of chiplet architectures, 2.5D/3D packaging, interposers, bridges, and known-good-die considerations. Experience using AI-enabled or agentic workflows to improve test development, debug, validation, documentation, or engineering productivity. Strong communication skills and demonstrated success leading and collaborating across geographically distributed teams. ACADEMIC CREDENTIALS Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr AMD